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1. 发明申请

US20090258463A1 METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY 有权
标题翻译：在半导体集成电路器件和半导体集成电路器件上制造不同厚度的硅 - 锗层的方法
公开(公告)号：US20090258463A1
公开(公告)日：2009-10-15
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

2. 发明申请

US20120228720A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS 有权
标题翻译：具有不同厚度硅 - 锗层的半导体集成电路器件
公开(公告)号：US20120228720A1
公开(公告)日：2012-09-13
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

3. 发明申请

US20100006906A1 Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot 审中-公开
标题翻译：半导体器件，单晶硅晶片和单晶硅锭
公开(公告)号：US20100006906A1
公开(公告)日：2010-01-14
申请号：US12458500
申请日：2009-07-14
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L29/04
CPC分类号： H01L27/0203 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L29/045 , H01L29/66628
摘要： A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a family direction.
摘要翻译：半导体器件包括单晶衬底和限定在单晶衬底中的有源区，其中有源区的长轴方向与<0,1,1>族方向对齐。

4. 发明申请

US20090170254A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090170254A1
公开(公告)日：2009-07-02
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

5. 发明授权

US08426916B2 Semiconductor integrated circuit devices having different thickness silicon-germanium layers 有权
标题翻译：具有不同厚度的硅 - 锗层的半导体集成电路器件
公开(公告)号：US08426916B2
公开(公告)日：2013-04-23
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/36
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

6. 发明授权

US08207033B2 Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby 有权
标题翻译：在半导体集成电路器件上制造不同厚度的硅 - 锗层的方法和由此制造的半导体集成电路器件
公开(公告)号：US08207033B2
公开(公告)日：2012-06-26
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

7. 发明授权

US07981750B2 Methods of fabrication of channel-stressed semiconductor devices 有权
标题翻译：通道应力半导体器件的制造方法
公开(公告)号：US07981750B2
公开(公告)日：2011-07-19
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
发明人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

8. 发明申请

US20080067545A1 Semiconductor device including field effect transistor and method of forming the same 审中-公开
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US20080067545A1
公开(公告)日：2008-03-20
申请号：US11898978
申请日：2007-09-18
申请人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Myung-sun Kim , Ji-hye Yi
发明人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Myung-sun Kim , Ji-hye Yi
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/26513 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a field effect transistor according to example embodiments may include a first semiconductor pattern disposed to fill a first recess region and a second semiconductor pattern disposed to fill a second recess region. The first recess region may be shallower than the second recess region and may be disposed adjacent to a channel region. Thus, sufficient stress may be supplied to the channel region to increase the mobility of holes or carriers in a channel and enhance a punchthrough characteristic.
摘要翻译：具有根据示例实施例的场效应晶体管的半导体器件可以包括设置成填充第一凹陷区域的第一半导体图案和设置成填充第二凹陷区域的第二半导体图案。第一凹部区域可以比第二凹部区域浅，并且可以设置在与沟道区域相邻的位置。因此，可以向通道区域提供足够的应力以增加通道中的空穴或载流子的迁移率并增强穿透特性。

9. 发明授权

US07791146B2 Semiconductor device including field effect transistor and method of forming the same 有权
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US07791146B2
公开(公告)日：2010-09-07
申请号：US11857157
申请日：2007-09-18
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

10. 发明授权

US08338261B2 Semiconductor device including field effect transistor and method of forming the same 有权
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US08338261B2
公开(公告)日：2012-12-25
申请号：US12851965
申请日：2010-08-06
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

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