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1. 发明授权

US07761757B2 Apparatus and method of setting test mode in semiconductor integrated circuit 有权
标题翻译：设置半导体集成电路测试模式的方法和设备
公开(公告)号：US07761757B2
公开(公告)日：2010-07-20
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
IPC分类号： G01R31/28
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

2. 发明申请

US20090121784A1 POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：掉电模式控制装置和具有该模式的DLL电路
公开(公告)号：US20090121784A1
公开(公告)日：2009-05-14
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： G05F1/10
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

3. 发明授权

US07868673B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07868673B2
公开(公告)日：2011-01-11
申请号：US12698606
申请日：2010-02-02
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

4. 发明授权

US07683684B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07683684B2
公开(公告)日：2010-03-23
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

5. 发明申请

US20090003101A1 APPARATUS AND METHOD OF SETTING TEST MODE IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：在半导体集成电路中设置测试模式的装置和方法
公开(公告)号：US20090003101A1
公开(公告)日：2009-01-01
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun Woo Lee , Dong-Suk Shin
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

6. 发明授权

US07598783B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07598783B2
公开(公告)日：2009-10-06
申请号：US11826401
申请日：2007-07-16
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

7. 发明申请

US20090058483A1 DUTY CYCLE CORRECTING CIRCUIT AND METHOD 审中-公开
标题翻译：占空比校正电路和方法
公开(公告)号：US20090058483A1
公开(公告)日：2009-03-05
申请号：US12200747
申请日：2008-08-28
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.
摘要翻译：占空比校正电路包括检测输出时钟信号的占空比以输出占空比检测信号的占空比检测器，输出通过根据占空比检测信号可变地延迟输入信号而获得的延迟时钟信号的可变延迟单元，以及脉冲宽度调制单元，当所述输入时钟信号和所述延迟时钟信号都处于高电平时，产生处于高电平的第一时钟信号，并且当所述第二时钟信号为输入时钟信号和延迟时钟信号处于高电平，其中脉冲宽度调制单元选择性地输出第一时钟信号或第二时钟信号作为输出时钟信号。

8. 发明申请

US20160197188A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20160197188A1
公开(公告)日：2016-07-07
申请号：US15071502
申请日：2016-03-16
申请人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
发明人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/51 , H01L27/11 , H01L29/45 , H01L27/088 , H01L29/08 , H01L29/165
CPC分类号： H01L27/1104 , H01L21/02532 , H01L21/02636 , H01L21/28247 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L27/088 , H01L27/1116 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/66636 , H01L29/7827 , H01L29/7833 , H01L29/7834 , H01L29/7845 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

9. 发明授权

US08637373B2 Transistors and methods of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08637373B2
公开(公告)日：2014-01-28
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

10. 发明授权

US08624629B2 Phase difference quantization circuit 有权
标题翻译：相位差量化电路
公开(公告)号：US08624629B2
公开(公告)日：2014-01-07
申请号：US13528148
申请日：2012-06-20
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： G01R25/00
CPC分类号： H03L7/089 , H03K5/131 , H03K5/14 , H03K2005/0028
摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.
摘要翻译：一种相位差量化电路的延迟值控制电路，其中相位差量化电路具有二进制权重的第一至第N（N是等于或大于2的整数）延迟单元。延迟值控制电路包括复制Ath（2 @ A @ N）延迟单元的复制延迟单元; 以及延迟控制单元，被配置为比较从延迟输入信号产生的第一输出信号与第一延迟单元的相位和从延迟输入信号而产生的第二输出信号的相位与Ath延迟单元和副本延迟单元，并且被配置为使用比较结果来控制Ath延迟单元的延迟值。

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