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1. 发明申请

US20160197188A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20160197188A1
公开(公告)日：2016-07-07
申请号：US15071502
申请日：2016-03-16
申请人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
发明人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/51 , H01L27/11 , H01L29/45 , H01L27/088 , H01L29/08 , H01L29/165
CPC分类号： H01L27/1104 , H01L21/02532 , H01L21/02636 , H01L21/28247 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L27/088 , H01L27/1116 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/66636 , H01L29/7827 , H01L29/7833 , H01L29/7834 , H01L29/7845 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

2. 发明授权

US08637373B2 Transistors and methods of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08637373B2
公开(公告)日：2014-01-28
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

3. 发明授权

US08624629B2 Phase difference quantization circuit 有权
标题翻译：相位差量化电路
公开(公告)号：US08624629B2
公开(公告)日：2014-01-07
申请号：US13528148
申请日：2012-06-20
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： G01R25/00
CPC分类号： H03L7/089 , H03K5/131 , H03K5/14 , H03K2005/0028
摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.
摘要翻译：一种相位差量化电路的延迟值控制电路，其中相位差量化电路具有二进制权重的第一至第N（N是等于或大于2的整数）延迟单元。延迟值控制电路包括复制Ath（2 @ A @ N）延迟单元的复制延迟单元; 以及延迟控制单元，被配置为比较从延迟输入信号产生的第一输出信号与第一延迟单元的相位和从延迟输入信号而产生的第二输出信号的相位与Ath延迟单元和副本延迟单元，并且被配置为使用比较结果来控制Ath延迟单元的延迟值。

4. 发明授权

US08344771B2 Delay locked loop of semiconductor integrated circuit and method for driving the same 失效
标题翻译：半导体集成电路的延迟锁定环路及其驱动方法
公开(公告)号：US08344771B2
公开(公告)日：2013-01-01
申请号：US12938081
申请日：2010-11-02
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0818
摘要： A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines.
摘要翻译：半导体集成电路的延迟锁定环（DLL）包括：第一延迟线，被配置为可变地延迟源时钟信号并输出锁定的时钟信号;相位比较器，被配置为将源时钟信号的相位与反馈时钟信号，被配置为可变延迟锁定的时钟信号的第二延迟线;配置成控制第一延迟线的第一延迟时间的第一延迟控制器，被配置为控制第二延迟线的最小延迟时间的第二延迟控制器以及操作模式控制器，被配置为响应于相位比较器的输出信号来控制第一和第二延迟控制器，以及根据延迟线的锁定状态的第一和第二延迟控制器的切换操作模式。

5. 发明申请

US20110306198A1 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20110306198A1
公开(公告)日：2011-12-15
申请号：US13157615
申请日：2011-06-10
申请人： Yong-Kuk Jeong , Dong-Suk Shin , Jong-Hun Kim , Hyun-Kwan Yu , Ki-eun Kim
发明人： Yong-Kuk Jeong , Dong-Suk Shin , Jong-Hun Kim , Hyun-Kwan Yu , Ki-eun Kim
IPC分类号： H01L21/28
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： A method of fabricating a semiconductor integrated circuit device includes forming a gate pattern on a semiconductor substrate, the gate pattern having a gate insulation film and a gate electrode. A spacer is formed on sidewalls of the gate pattern. A silicide layer is formed by a silicide process on at least one portion of the semiconductor substrate exposed by the gate pattern and the spacer, the silicide layer being formed using a silicide process. A stress buffer layer is formed on a resultant structure having the silicide layer. A stress film is formed on the stress buffer layer.
摘要翻译：一种制造半导体集成电路器件的方法包括在半导体衬底上形成栅极图案，栅极图案具有栅极绝缘膜和栅电极。在栅极图案的侧壁上形成间隔物。硅化物层通过硅化物工艺在由栅极图案和间隔物暴露的半导体衬底的至少一部分上形成，硅化物层使用硅化物工艺形成。在具有硅化物层的所得结构上形成应力缓冲层。在应力缓冲层上形成应力膜。

6. 发明申请

US20110291725A1 DUTY DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME 失效
标题翻译：负载检测电路和占空比校正电路，包括它们
公开(公告)号：US20110291725A1
公开(公告)日：2011-12-01
申请号：US12832092
申请日：2010-07-08
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03K3/017
CPC分类号： G11C7/22 , G11C7/222 , H03K5/1565 , H03K9/08
摘要： A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.
摘要翻译：占空比校正电路包括占空比调整电路，其被配置为通过响应于占空比调整代码调整输入时钟的占空比来产生输出时钟;占空比检测电路，被配置为测量高脉冲宽度与在每个更新周期的输出时钟的低脉冲的宽度，并且生成与测量值相对应的占空比检测码;累加电路，被配置为通过累加在每次更新时输出的占空比检测码的值来生成占空比调整码周期，以及切换数量调整电路，被配置为根据输出时钟的频率来调整输出时钟的切换次数，该调整确定更新周期。

7. 发明授权

US07981784B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07981784B2
公开(公告)日：2011-07-19
申请号：US12381175
申请日：2009-03-09
申请人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
发明人： Dong-Suk Shin , Ki-Chul Kim , Jung-Deog Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.
摘要翻译：隔离区形成在衬底上以限定有源区。在有源区上形成栅电极。间隔结构形成在栅电极的侧壁上。在栅电极上形成栅极硅化物层，并且在与栅电极相邻的有源区上形成源极/漏极硅化物层。栅极硅化物层的上部和间隔物结构的一部分被同时去除以形成间隔物结构图案和栅极硅化物层图案。形成应力层以覆盖栅电极和间隔结构图案。

8. 发明授权

US07973309B2 TEG pattern for detecting void in device isolation layer and method of forming the same 失效
标题翻译：用于检测器件隔离层中空隙的TEG图案及其形成方法
公开(公告)号：US07973309B2
公开(公告)日：2011-07-05
申请号：US12435161
申请日：2009-05-04
申请人： Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
发明人： Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
IPC分类号： H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.
摘要翻译：提供了用于检测器件隔离层中的空隙的测试元件组（TEG）图案。 TEG图案包括彼此平行并在第一方向上延伸的有源区域，分离有源区域的器件隔离层，跨过器件隔离层形成的第一接触和接触的第一有源区域器件隔离层的表面，以及跨过器件隔离层形成的第二接触和接触器件隔离层的另一表面的第二有源区。

9. 发明申请

US20100167533A1 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100167533A1
公开(公告)日：2010-07-01
申请号：US12647806
申请日：2009-12-28
申请人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park , Jun-Jung Kim , Tae-Gyun Kim
发明人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park , Jun-Jung Kim , Tae-Gyun Kim
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/78 , H01L29/7843
摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.
摘要翻译：制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

10. 发明申请

US20090283764A1 TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME 失效
标题翻译：用于检测设备隔离层中的空穴的TEG图案及其形成方法
公开(公告)号：US20090283764A1
公开(公告)日：2009-11-19
申请号：US12435161
申请日：2009-05-04
申请人： Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
发明人： Tae-Gyun Kim , Dong-Suk Shin , Joo-Won Lee , Ha-Jin Lim
IPC分类号： H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.
摘要翻译：提供了用于检测器件隔离层中的空隙的测试元件组（TEG）图案。 TEG图案包括彼此平行并在第一方向上延伸的有源区域，分离有源区域的器件隔离层，跨过器件隔离层形成的第一接触和接触的第一有源区域器件隔离层的表面，以及跨过器件隔离层形成的第二接触和接触器件隔离层的另一表面的第二有源区。

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