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1. 发明申请

US20090121784A1 POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：掉电模式控制装置和具有该模式的DLL电路
公开(公告)号：US20090121784A1
公开(公告)日：2009-05-14
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： G05F1/10
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

2. 发明授权

US07868673B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07868673B2
公开(公告)日：2011-01-11
申请号：US12698606
申请日：2010-02-02
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

3. 发明授权

US07683684B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07683684B2
公开(公告)日：2010-03-23
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

4. 发明授权

US07761757B2 Apparatus and method of setting test mode in semiconductor integrated circuit 有权
标题翻译：设置半导体集成电路测试模式的方法和设备
公开(公告)号：US07761757B2
公开(公告)日：2010-07-20
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
IPC分类号： G01R31/28
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

5. 发明授权

US07598783B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07598783B2
公开(公告)日：2009-10-06
申请号：US11826401
申请日：2007-07-16
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

6. 发明申请

US20090058483A1 DUTY CYCLE CORRECTING CIRCUIT AND METHOD 审中-公开
标题翻译：占空比校正电路和方法
公开(公告)号：US20090058483A1
公开(公告)日：2009-03-05
申请号：US12200747
申请日：2008-08-28
申请人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
发明人： Dong-Suk Shin , Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.
摘要翻译：占空比校正电路包括检测输出时钟信号的占空比以输出占空比检测信号的占空比检测器，输出通过根据占空比检测信号可变地延迟输入信号而获得的延迟时钟信号的可变延迟单元，以及脉冲宽度调制单元，当所述输入时钟信号和所述延迟时钟信号都处于高电平时，产生处于高电平的第一时钟信号，并且当所述第二时钟信号为输入时钟信号和延迟时钟信号处于高电平，其中脉冲宽度调制单元选择性地输出第一时钟信号或第二时钟信号作为输出时钟信号。

7. 发明授权

US07605623B2 Semiconductor memory apparatus with a delay locked loop circuit 有权
标题翻译：具有延迟锁定环路的半导体存储装置
公开(公告)号：US07605623B2
公开(公告)日：2009-10-20
申请号：US11824428
申请日：2007-06-29
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/087 , H03L7/095
摘要： A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.
摘要翻译：一种半导体存储装置，包括：延迟线，被配置为延迟参考时钟;第一延迟块，被配置为延迟反馈时钟;第一相位比较器，被配置为将参考时钟与第一延迟块的输出进行比较;第二延迟块，延迟参考时钟;第二相位比较器，被配置为将反馈时钟与第二延迟块的输出进行比较;延迟控制器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟线的延迟量，延迟模型，被配置为延迟延迟线的输出通过建模的延迟时间以产生反馈时钟;以及锁定检测器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟控制器。

8. 发明申请

US20080054964A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080054964A1
公开(公告)日：2008-03-06
申请号：US11819783
申请日：2007-06-29
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/0818
摘要： A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
摘要翻译：半导体存储器件包括用于校正延迟锁定时钟信号的占空比的延迟锁定环路。半导体存储器件包括延迟锁定电路，占空比校正电路和时钟同步电路。延迟锁定电路通过将系统时钟延迟预定时间来输出延迟锁定时钟。占空比校正电路通过校正延迟锁定时钟的占空比来输出第一时钟，其中延迟锁定时钟的高电平到低电平周期的比例根据第一时钟的第二边沿和来自第一时钟的第二时钟的信号。时钟同步电路将第一时钟的第一边沿与第二时钟的第一边沿同步。

9. 发明授权

US07994831B2 Semiconductor integrated circuit and method of controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US07994831B2
公开(公告)日：2011-08-09
申请号：US12176217
申请日：2008-07-18
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0802 , H03L7/087 , H03L7/095
摘要： A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.
摘要翻译：公开了一种半导体集成电路。所公开的本发明的半导体集成电路包括响应于检测外部的相位变化范围的结果来控制是否在断电模式的入口处激活DLL的DLL（延迟锁定环路）时钟信号在预定范围内，以及DLL块，其将提供将参考时钟信号与反馈时钟信号进行比较的结果提供给DLL控制器，并且还响应于参考时钟提供周期性更新的延迟锁定时钟信号信号，在来自DLL控制器的激活的输出信号的控制下。

10. 发明授权

US07755405B2 DLL circuit and method of controlling the same 失效
标题翻译： DLL电路及其控制方法
公开(公告)号：US07755405B2
公开(公告)日：2010-07-13
申请号：US12172137
申请日：2008-07-11
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal.
摘要翻译：延迟锁定环路（DLL）电路包括：第一延迟控制单元，被配置为响应于第一相位检测信号产生第一延迟控制信号，以控制第一延迟线的延迟量并输出第一延迟量信息信号，第二延迟控制单元，被配置为响应于第二相位检测信号产生第二延迟控制信号，以控制第二延迟线的延迟量并输出第二延迟量信息信号，并且控制第二延迟控制信号的延迟量延迟线响应于第一延迟控制信号和半周期信息信号，半周期检测单元被配置为接收第一延迟量信息信号和第二延迟量信息信号以提取参考时钟信号的半周期信息，从而生成半周期信息信号，以及占空比校正单元，被配置为组合来自第一d的输出时钟信号 elay线和来自第二延迟线的输出时钟信号，从而输出占空比校正时钟信号。

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