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1. 发明授权

US07639993B1 Power supply circuitry for data signal transceivers on integrated circuits 有权
标题翻译：集成电路上数据信号收发器的电源电路
公开(公告)号：US07639993B1
公开(公告)日：2009-12-29
申请号：US11295391
申请日：2005-12-05
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
IPC分类号： H04B1/04
CPC分类号： H04L7/033
摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
摘要翻译：集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

2. 发明授权

US08189729B2 Wide range and dynamically reconfigurable clock data recovery architecture 有权
标题翻译：宽范围和动态可重构的时钟数据恢复架构
公开(公告)号：US08189729B2
公开(公告)日：2012-05-29
申请号：US11329197
申请日：2006-01-09
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03K19/17732 , H03K19/17744 , H03L7/10 , H04L7/0004 , H04L7/033
摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
摘要翻译：宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。为了支持广泛的数据速率，CDR架构包括多个操作参数。这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。可以在不关闭电路或PLD的情况下动态重新编程参数。这允许CDR电路在各种标准和协议之间进行即时切换。

3. 发明授权

US08416845B1 Decision feedback equalization for variable input amplitude 有权
标题翻译：用于可变输入幅度的判决反馈均衡
公开(公告)号：US08416845B1
公开(公告)日：2013-04-09
申请号：US11484285
申请日：2006-07-11
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03K5/1532
摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.
摘要翻译：提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。抽头系数可以由均衡电路自动调整。

4. 发明授权

US07782935B1 Half-rate DFE with duplicate path for high data-rate operation 有权
标题翻译：具有高数据速率操作的重复路径的半速率DFE
公开(公告)号：US07782935B1
公开(公告)日：2010-08-24
申请号：US11514490
申请日：2006-08-31
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H04L25/03878 , H04L2025/0349
摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.
摘要翻译：提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。可以使用以输入信号数据速率的一半工作的两个延迟链电路。更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

5. 发明授权

US07355449B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07355449B1
公开(公告)日：2008-04-08
申请号：US11345709
申请日：2006-02-01
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh Patel
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh Patel
IPC分类号： H03K19/094
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

6. 发明授权

US08743943B2 High-speed data reception circuitry and methods 有权
标题翻译：高速数据接收电路和方法
公开(公告)号：US08743943B2
公开(公告)日：2014-06-03
申请号：US11192539
申请日：2005-07-28
申请人： Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03573
摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.
摘要翻译：用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

7. 发明授权

US07702011B2 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US07702011B2
公开(公告)日：2010-04-20
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

8. 发明授权

US07324031B1 Dynamic bias circuit 有权
标题翻译：动态偏置电路
公开(公告)号：US07324031B1
公开(公告)日：2008-01-29
申请号：US11355678
申请日：2006-02-15
申请人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
发明人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
IPC分类号： H03M1/66
CPC分类号： G11C7/12 , G11C7/1045 , H03M1/662
摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.
摘要翻译：偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。通过时域复用方案，D2A可由均衡电路的控制旋钮共享。偏置电路包括还耦合到主寄存器框架的解码器。还包括一个输出使能逻辑模块。当数据链中的数据根据时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。还提供了一种通过偏置电路调整信号的方法。

9. 发明授权

US07557615B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07557615B1
公开(公告)日：2009-07-07
申请号：US12069353
申请日：2008-02-08
申请人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
发明人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

10. 发明授权

US08406258B1 Apparatus and methods for low-jitter transceiver clocking 有权
标题翻译：低抖动收发器时钟的装置和方法
公开(公告)号：US08406258B1
公开(公告)日：2013-03-26
申请号：US12752984
申请日：2010-04-01
申请人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
发明人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
IPC分类号： H04J3/06
CPC分类号： H03M9/00 , H03K19/1776 , H04J3/047 , H04J3/0685
摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。还公开了其它实施例和特征。

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