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1. 发明授权

US07149914B1 Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths 有权
标题翻译：时钟数据恢复电路和具有动态可调节带宽的锁相环电路
公开(公告)号：US07149914B1
公开(公告)日：2006-12-12
申请号：US10672901
申请日：2003-09-26
申请人： Kazi Asaduzzaman , Wilson Wong , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Wilson Wong , Sergey Shumarayev
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , G06F1/24
CPC分类号： H03L7/087 , H03L7/107 , H03L7/18 , H04L7/0008 , H04L7/033
摘要： Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.
摘要翻译：时钟数据恢复（CDR）电路或锁相环（PLL）电路可以提供动态可调的带宽。可以提供一个CDR电路或PLL电路以支持多个系统或协议，给定系统或协议的多个参数要求，以及给定系统或协议内的输入频率或数据速率的变化。这些参数可以包括抖动（例如，抖动容限，抖动传输，抖动产生），主要噪声源和锁定时间。当电路正在处理数据时，控制信号可用于动态调整CDR电路或PLL电路的带宽。控制信号可以由PLD，处理器，PLD外部的电路或用户输入来设置。

2. 发明授权

US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features 有权
标题翻译：时钟和数据恢复电路，具有自动速度协商和其他可能的功能
公开(公告)号：US08811555B2
公开(公告)日：2014-08-19
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

3. 发明授权

US07619451B1 Techniques for compensating delays in clock signals on integrated circuits 有权
标题翻译：补偿集成电路时钟信号延迟的技术
公开(公告)号：US07619451B1
公开(公告)日：2009-11-17
申请号：US11670971
申请日：2007-02-03
申请人： Tim Tri Hoang , Sergey Shumarayev , Kazi Asaduzzaman , Wanli Chang , Mian Z. Smith , Kang-Wei Lai , Leon Zheng
发明人： Tim Tri Hoang , Sergey Shumarayev , Kazi Asaduzzaman , Wanli Chang , Mian Z. Smith , Kang-Wei Lai , Leon Zheng
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , G06F1/12 , H03L7/081 , H03L7/0812
摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.
摘要翻译：提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

4. 发明授权

US08671305B1 Techniques for adjusting periodic signals based on data detection 有权
标题翻译：基于数据检测调整周期信号的技术
公开(公告)号：US08671305B1
公开(公告)日：2014-03-11
申请号：US13175604
申请日：2011-07-01
申请人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
发明人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04B10/6165 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/14 , H04L7/0004 , H04L7/0083 , H04L7/033
摘要： A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.
摘要翻译：电路包括相位检测器电路，相位频率检测器电路，数据检测电路，多路复用器电路和时钟信号发生电路。相位检测器电路可操作以基于数据信号和第一周期信号产生第一相位检测信号。相位频率检测器电路可操作以基于第二和第三周期信号产生第二相位检测信号。数据检测电路可操作以基于第一相位检测信号产生数据检测信号。多路复用器电路可操作以基于数据检测信号提供第一和第二相位检测信号中的一个作为选择的信号。周期信号产生电路可操作以基于所选择的信号来调整第一和第二周期信号的相位。

5. 发明授权

US07555087B1 Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector 有权
标题翻译：时钟数据恢复电路，动态支持数据速率的变化和动态调整的PPM探测器
公开(公告)号：US07555087B1
公开(公告)日：2009-06-30
申请号：US12027909
申请日：2008-02-07
申请人： Kazi Asaduzzaman , Wilson Wong
发明人： Kazi Asaduzzaman , Wilson Wong
IPC分类号： H04L7/02
CPC分类号： H04L7/0338 , H03L7/0807 , H03L7/087
摘要： Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.
摘要翻译：可以为时钟数据恢复（CDR）电路提供动态支持，以改变由不同协议的接口引起的数据速率。以参考时钟模式和数据模式工作的CDR电路可以由两个控制信号控制，这两个信号指示CDR电路在参考时钟模式和数据模式之间自动切换，仅在参考时钟模式下工作，或仅在数据模式。控制信号可由可编程逻辑器件（PLD），PLD外部电路或用户输入设置。也可以在CDR电路中提供动态可调节的百万分之一（PPM）检测器，以在参考时钟模式完成期间处理数据时发出信号。

6. 发明授权

US07089444B1 Clock and data recovery circuits 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US07089444B1
公开(公告)日：2006-08-08
申请号：US10670147
申请日：2003-09-24
申请人： Kazi Asaduzzaman , Wilson Wong
发明人： Kazi Asaduzzaman , Wilson Wong
IPC分类号： G06F1/04
CPC分类号： H04L7/033 , H04L7/0008
摘要： Clock and data recovery circuitry is provided that is used in integrated circuits such as programmable logic device integrated circuits. The clock and data recovery circuitry may recover digital data and an embedded clock from a high-speed differential input data stream. The clock and data recovery circuitry may have automatic mode switching capabilities. When operated in reference mode, the clock and data recovery circuit may use a first phase-locked loop to lock onto a reference clock. When operated in data mode, the clock and data recovery circuit may use a second phase-locked loop to lock onto the phase of the differential data stream. A control circuit may automatically switch the clock and data recovery circuit between the reference mode and the data mode. Override signals may be used to force the clock and data recovery circuit out of the automatic mode and into either the reference or data mode.
摘要翻译：提供了用于诸如可编程逻辑器件集成电路的集成电路中的时钟和数据恢复电路。时钟和数据恢复电路可以从高速差分输入数据流恢复数字数据和嵌入时钟。时钟和数据恢复电路可以具有自动模式切换功能。当在参考模式下操作时，时钟和数据恢复电路可以使用第一锁相环锁定到参考时钟。当在数据模式下操作时，时钟和数据恢复电路可以使用第二锁相环来锁定差分数据流的相位。控制电路可以在参考模式和数据模式之间自动切换时钟和数据恢复电路。可以使用覆盖信号强制时钟和数据恢复电路脱离自动模式并进入参考或数据模式。

7. 发明授权

US07728674B1 Voltage-controlled oscillator methods and apparatus 失效
标题翻译：压控振荡器的方法和装置
公开(公告)号：US07728674B1
公开(公告)日：2010-06-01
申请号：US11437558
申请日：2006-05-19
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译：提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

8. 发明授权

US07557615B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07557615B1
公开(公告)日：2009-07-07
申请号：US12069353
申请日：2008-02-08
申请人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
发明人： Thungoc M. Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh H. Patel
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

9. 发明授权

US07532029B1 Techniques for reconfiguring programmable circuit blocks 有权
标题翻译：重新配置可编程电路块的技术
公开(公告)号：US07532029B1
公开(公告)日：2009-05-12
申请号：US11737079
申请日：2007-04-18
申请人： Kazi Asaduzzaman , Leon Zheng , Sergey Shumarayev , Tim Tri Hoang
发明人： Kazi Asaduzzaman , Leon Zheng , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K19/173 , H03L7/00
CPC分类号： H03K19/1733 , H03K19/17752 , H03L7/081 , H03L7/0898 , H03L7/093 , H03L7/0996 , H03L7/18
摘要： Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.
摘要翻译：提供技术用于在用户模式期间动态地重新配置集成电路上的可编程电路块。在配置模式下，第一个配置位从第一个配置扫描寄存器加载到第二个配置扫描寄存器中。第一个配置位用于配置可编程电路块的可编程设置。在用户模式期间，第二配置位从引脚传输到第二配置扫描寄存器，而不通过第一配置扫描寄存器传输第二配置位。第二个配置位用于在用户模式期间重新配置可编程电路块的可编程设置。此外，相移电路可以通过选择不同的输入时钟信号来动态地移位输出时钟信号的相位。相移电路具有允许高频时钟信号的相位被移位而不引起时钟信号的毛刺的延迟电路。

10. 发明申请

US20070013411A1 Apparatus and methods for programmable slew rate control in transmitter circuits 审中-公开
标题翻译：发射机电路中可编程转换速率控制的装置和方法
公开(公告)号：US20070013411A1
公开(公告)日：2007-01-18
申请号：US11183288
申请日：2005-07-14
申请人： Kazi Asaduzzaman , Sergey Shumarayev , Thungoc Tran , Wilson Wong , Rakesh Patel
发明人： Kazi Asaduzzaman , Sergey Shumarayev , Thungoc Tran , Wilson Wong , Rakesh Patel
IPC分类号： H03K19/094
CPC分类号： H03K17/164
摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.
摘要翻译：可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。描述了用于提供可变转换速率控制的驱动电路和方法。可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。预驱动器电路可以被延迟匹配以保持信号质量。还描述了其它电路和方法。

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