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1. 发明授权

US5596583A Test circuitry, systems and methods 失效
标题翻译：测试电路，系统和方法
公开(公告)号：US5596583A
公开(公告)日：1997-01-21
申请号：US734344
申请日：1991-07-19
申请人： William R. Krenik , Louis J. Izzi , Chenwei J. Yin
发明人： William R. Krenik , Louis J. Izzi , Chenwei J. Yin
IPC分类号： G11C29/14 , G11C29/48 , G01R31/28
CPC分类号： G11C29/48 , G11C29/14
摘要： Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).
摘要翻译：提供了测试电路（90），其包括多路复用器（118），用于选择性地接收定义由所述测试电路执行的测试功能的多个位控制字，并用于从所述测试电路输出数据。提供多个数字数据输入（96）用于接收数字数据的多位字，并且提供多个模拟数据输入（98）用于接收模拟数据。寄存器（120）耦合到多路复用器（118），用于存储由多路复用器（118）接收的多个位字之一。控制电路（122）耦合到寄存器（120），用于控制由保持在寄存器（120）中的控制字定义的测试功能的执行。第一测试电路（112）耦合到数字数据输入（96）和控制电路（122），用于将数字数据输入（96）接收的数字数据字传送到多路复用器（118），以响应于所述第一控制字控制字被保存在寄存器（120）中。

2. 发明授权

US5313231A Color palette device having big/little endian interfacing, systems and methods 失效
标题翻译：调色板装置具有大/小端接，系统和方法
公开(公告)号：US5313231A
公开(公告)日：1994-05-17
申请号：US856431
申请日：1992-03-24
申请人： Chenwei J. Yin , Richard C. Nail , Louis J. Izzi , Edison H. Chiu
发明人： Chenwei J. Yin , Richard C. Nail , Louis J. Izzi , Edison H. Chiu
IPC分类号： G06F7/76 , G09G5/02 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G09G1/28
CPC分类号： G06F7/768 , G09G5/026 , G09G5/06 , G09G5/363 , G09G5/395
摘要： A color palette is provided having a plurality input terminals for receiving a plurality of bits of data having an order. A two color path is included which comprises first circuitry coupled to the input terminals for selectively reversing the order of the plurality of bits of data. Second circuitry is coupled to the first circuitry and is operable in a first mode to pass all of the plurality of bits of data received from the first circuitry and in a second mode has at least one word comprising selected ones of the plurality of bits, the selected ones of the bits having a bit order. The third circuitry is provided coupled to the second circuitry and operable to pass all of the bits of data received from the second circuitry in the first mode and operable to selectively reverse the ordering of the selected ones of the bits and pass be at least one word received from the second circuitry in the second mode. The fourth circuitry is further provided coupled to the third circuitry inoperable to receive bits of data passed from the circuitry and select for output as at least one word of true color data at least some of the bits.
摘要翻译：提供一种调色板，具有用于接收具有顺序的多个数据位的多个输入端子。包括两色路径，其包括耦合到输入端的第一电路，用于选择性地反转多个数据位的顺序。第二电路被耦合到第一电路，并且可以在第一模式中操作以通过从第一电路接收的所有多个数据位，并且在第二模式中具有包括多个位中的选定位的至少一个字，具有位顺序的选择的位。提供第三电路，其耦合到第二电路并且可操作以在第一模式中传送从第二电路接收的所有数据位，并且可操作以选择性地反转所选择的位的顺序并将其传递至少一个字在第二模式中从第二电路接收。第四电路进一步提供为耦合到第三电路，其不可操作地接收从电路传送的数据位，并且选择输出作为至少一些位的至少一个真彩色数据字。

3. 发明授权

US5371517A Video interface palette, systems and method 失效
标题翻译：视频界面调色板，系统和方法
公开(公告)号：US5371517A
公开(公告)日：1994-12-06
申请号：US791757
申请日：1991-11-08
申请人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
发明人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
IPC分类号： G06F11/00 , G09G5/06 , G09G5/18 , G09G1/28
CPC分类号： G06F11/006 , G09G5/06 , G09G5/18
摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.
摘要翻译：响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。电路响应于消隐数据选择性地启用和禁用移位时钟。响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。电路将彩色数据字选择性地写入这些多个位置。电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。

4. 发明授权

US5590134A Test circuits and method for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state 失效
标题翻译：通过累积特定逻辑状态的位的具有存储器和非存储器电路的集成电路的测试电路和方法
公开(公告)号：US5590134A
公开(公告)日：1996-12-31
申请号：US477213
申请日：1995-06-07
申请人： Chenwei J. Yin
发明人： Chenwei J. Yin
IPC分类号： G09G3/00 , G09G5/06 , G09G5/08 , G09G5/36 , G09G5/39 , G11C29/00
CPC分类号： G09G5/363 , G09G3/006 , G09G5/06 , G09G5/39 , G09G2330/12 , G09G2340/12 , G09G5/08
摘要： An integrated circuit includes read/write memory and non-memory circuitry. A detector generates a count of the number of bits of each data words recalled from the memory having a predetermined logic state. An adder accumulates the count for plural data words over a period of time into a count register. The integrated circuit may be tested by lading each data word of the read/write memory with a first logic state and repeatedly addressing said read/write memory circuitry with a predetermined number of each possible address in sequence. The resulting count in the count register is compared with an expected count. The integrated circuit may also be tested by loading a predetermined addressable storage location with another logic state while loading all other addressable storage locations with the first logic state and repeatedly addressing the predetermined addressable storage location. The resulting count in the count register is compared with another expected count. The non-memory circuitry is preferably digital to analog converters, whose outputs may be compared to test their operation.
摘要翻译：集成电路包括读/写存储器和非存储器电路。检测器产生从具有预定逻辑状态的存储器回忆的每个数据字的位数的计数。加法器将一段时间内的多个数据字的计数累加到计数寄存器中。可以通过以第一逻辑状态提取读/写存储器的每个数据字来测试集成电路，并且以预定数量的每个可能的地址依次重复寻址所述读/写存储器电路。将计数寄存器中的结果计数与预期计数进行比较。也可以通过在具有第一逻辑状态加载所有其他可寻址存储位置并重复寻址预定的可寻址存储位置的同时加载具有另一逻辑状态的预定可寻址存储位置来测试集成电路。将计数寄存器中的结果计数与另一个预期计数进行比较。非存储器电路优选地是数模转换器，其输出可以被比较以测试它们的操作。

5. 发明授权

US5446482A Flexible graphics interface device switch selectable big and little endian modes, systems and methods 失效
标题翻译：灵活的图形界面设备开关选择大和小端模式，系统和方法
公开(公告)号：US5446482A
公开(公告)日：1995-08-29
申请号：US792503
申请日：1991-11-13
申请人： Jerry R. Van Aken , Chenwei J. Yin
发明人： Jerry R. Van Aken , Chenwei J. Yin
IPC分类号： G09G5/02 , G06T11/00 , G09G5/06 , G09G5/36 , G09G1/28
CPC分类号： G09G5/06
摘要： A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the n.sup.th first AND gate 126 coupled to the n.sup.th one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an n.sup.th one of the second AND gates 128 coupled to a (j-n+1).sup.th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an m.sup.th one of the OR gates 130 being coupled to the output of an m.sup.th one of the first AND gate 126, the second input port of an n.sup.th one of the OR gates 130 coupled to the output of the n.sup.th one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j.
摘要翻译：提供一个电路83,97用于选择性地将从大端和小端格式选择的格式接收的数据解析为大端和小端格式的另一种格式，并且包括j个顺序数据输入的阵列用于接收以预选的大端和小端格式格式化的数据的j位字的终端。提供了j个顺序排列的第一与门126的阵列，每个第一与门126具有第一和第二输入端口和输出端口，第n个第一与门126的第一输入端口耦合到第n个输入端子，第一与门126的第二输入端口耦合到控制信号。提供了j个顺序排列的第二与门128的阵列，并且每个第二与门128具有第一和第二输入端口的第一和第二输入端口和第二输入端口，第二输入端口与第 -n + 1）个第一输入端，第二与门128的第二输入端耦合到第二控制。提供了具有第一和第二输入端口和输出端口的j个顺序OR门130的阵列，或门130的第m个的第一输入端口耦合到第一与门第一个的输出端 126是与第二AND门128的第n个的输出耦合的或门130中第n个的第二输入端口。其中j是辅音，n是1和j之间的变量，m是变量在1和j之间。

6. 发明授权

US5400057A Internal test circuits for color palette device 失效
标题翻译：调色板装置的内部测试电路
公开(公告)号：US5400057A
公开(公告)日：1995-03-21
申请号：US116476
申请日：1993-09-03
申请人： Chenwei J. Yin
发明人： Chenwei J. Yin
IPC分类号： G09G3/00 , G09G5/06 , G09G5/08 , G09G5/36 , G09G5/39
CPC分类号： G09G5/363 , G09G3/006 , G09G5/06 , G09G5/39 , G09G2330/12 , G09G2340/12 , G09G5/08
摘要： An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states including a first logic state and at least one other logic state. A semiconductor chip package has pins connected to the chip circuitry. Accumulator circuitry on-chip and connected to the chip circuitry generates a count of the the number of locations in the set that have the first logic state. The semiconductor chip package has pins connected to the chip circuitry and accumulator circuitry for external access to the count. Other integrated circuits, palette devices, computer graphics systems and methods are disclosed.
摘要翻译：一种包括半导体芯片和芯片电路的集成电路，其包括全部在半导体芯片上制造的存储器电路和附加非存储器电路。芯片电路具有定义的一组位置，其具有包括第一逻辑状态和至少一个其他逻辑状态的逻辑状态。半导体芯片封装具有连接到芯片电路的引脚。片上并连接到芯片电路的累加器电路产生具有第一逻辑状态的集合中的位置数的计数。半导体芯片封装具有连接到芯片电路和累加器电路的引脚，用于外部访问计数。公开了其他集成电路，调色板装置，计算机图形系统和方法。

7. 发明授权

US5717697A Test circuits and methods for integrated circuit having memory and non-memory circuits by accumulating bits of a particular logic state 失效
标题翻译：通过累积特定逻辑状态的位的具有存储器和非存储器电路的集成电路的测试电路和方法
公开(公告)号：US5717697A
公开(公告)日：1998-02-10
申请号：US934598
申请日：1992-08-24
申请人： Chenwei J. Yin
发明人： Chenwei J. Yin
IPC分类号： G09G3/00 , G09G5/06 , G09G5/08 , G09G5/36 , G09G5/39 , G06F11/10
CPC分类号： G09G5/363 , G09G3/006 , G09G5/06 , G09G5/39 , G09G2330/12 , G09G2340/12 , G09G5/08
摘要： An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states including a first logic state and at least one other logic state. A semiconductor chip package has pins connected to the chip circuitry. Accumulator circuitry on-chip and connected to the chip circuitry generates a count of the number of locations in the set that have the first logic state. The semiconductor chip package has pins connected to the chip circuitry and accumulator circuitry for external access to the count. Other integrated circuits, palette devices, computer graphics systems and methods are disclosed.
摘要翻译：一种包括半导体芯片和芯片电路的集成电路，其包括全部在半导体芯片上制造的存储器电路和附加非存储器电路。芯片电路具有定义的一组位置，其具有包括第一逻辑状态和至少一个其他逻辑状态的逻辑状态。半导体芯片封装具有连接到芯片电路的引脚。片上并连接到芯片电路的累加器电路产生具有第一逻辑状态的集合中的位置数的计数。半导体芯片封装具有连接到芯片电路和累加器电路的引脚，用于外部访问计数。公开了其他集成电路，调色板装置，计算机图形系统和方法。

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