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    • 3. 发明授权
      US5371517A Video interface palette, systems and method 失效
    • Video interface palette, systems and method
    • 视频界面调色板，系统和方法
    • US5371517A
    • 1994-12-06
    • US791757
    • 1991-11-08
    • Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
    • Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
    • G06F11/00 , G09G5/06 , G09G5/18 , G09G1/28
    • G06F11/006 , G09G5/06 , G09G5/18
    • A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.
    • 响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。 电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。 电路响应于消隐数据选择性地启用和禁用移位时钟。 响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。 电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。 响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。 电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。 电路将彩色数据字选择性地写入这些多个位置。 电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。 电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20080077771A1 Long Instruction Word Controlling Plural Independent Processor Operations 审中-公开
    • Long Instruction Word Controlling Plural Independent Processor Operations
    • US20080077771A1
    • 2008-03-27
    • US11930652
    • 2007-10-31
    • Karl Guttag , Christopher Read , Keith Balmer
    • Karl Guttag , Christopher Read , Keith Balmer
    • G06F9/30
    • G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
    • This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210). The status register (210) is set by a prior output of the arithmetic logic unit (230) and the instruction may specify some of the status bits protect from change. The address unit (120) preferably includes a plurality of base address registers (611), a full adder (615) and a left shifter (614). The full adder (615) may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder (615) output may update the base address register (611), either before supply of the address or following supply of the address. The index may be recalled from an index register (612) or an immediate value. In the preferred embodiment of this invention, the data unit (110) including the data registers (200), the multiplication unit (220) and the arithmetic logic unit (230), the address unit (120) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US4718024A Graphics data processing apparatus for graphic image operations upon data of independently selectable pitch 失效
    • Graphics data processing apparatus for graphic image operations upon data of independently selectable pitch
    • 图形数据处理装置，用于对独立可选择的音调的数据进行图形图像操作
    • US4718024A
    • 1988-01-05
    • US795158
    • 1985-11-05
    • Karl Guttag , Mike Asal , Mark Novak
    • Karl Guttag , Mike Asal , Mark Novak
    • G06T1/60 , G09G5/391 , G09G5/393 , G06F15/00
    • G09G5/391 , G06T1/60 , G09G5/393
    • The graphics data processing apparatus performs graphic data processing operations by combining data from two image arrays in accordance with a predetermined operation. This raster operation involves forming an image array having a pixel color code for each pixel of the combined image array formed from a combination of the color codes of corresponding pixels of the source and destination image arrays. The present invention includes a pair of data registers which define the difference in memory address between vertically adjacent pixels for the respective image arrays. This difference in memory address between vertically adjacent pixels is called the pitch and corresponds generally to the width of the display image in address space when any horizontal blanking interval is taken into account. In the present invention such raster operations can be performed on data which is stored in formats of differing pitch. This capability enables standard typefaces and icons to be stored in a default pitch while still being usable for a variety of display applications. In addition, even in the case in which both the source and destination pitches are the same, the capability for controlling the pitch for raster operations permits the same graphics data processing apparatus to operate in a variety of display applications. Thus the flexibility of operation and ease of application to differing graphics display problems is enhanced.
    • 图形数据处理装置通过根据预定的操作组合来自两个图像阵列的数据来执行图形数据处理操作。 该光栅操作涉及形成具有由源和目的图像阵列的相应像素的颜色代码的组合形成的组合图像阵列的每个像素的像素颜色代码的图像阵列。 本发明包括一对数据寄存器，其定义用于各个图像阵列的垂直相邻像素之间的存储器地址的差异。 当考虑到任何水平消隐间隔时，垂直相邻像素之间的存储器地址的差异被称为间距，并且通常对应于地址空间中的显示图像的宽度。 在本发明中，可以对以不同音调的格式存储的数据执行这样的光栅操作。 该功能使标准字体和图标能够以默认音高存储，同时仍可用于各种显示应用。 此外，即使在源极和目标间距都相同的情况下，用于控制光栅操作的间距的能力允许相同的图形数据处理装置在各种显示应用中操作。 因此，提高了操作的灵活性和易于应用于不同图形显示问题。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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