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1. 发明授权

US5371517A Video interface palette, systems and method 失效
标题翻译：视频界面调色板，系统和方法
公开(公告)号：US5371517A
公开(公告)日：1994-12-06
申请号：US791757
申请日：1991-11-08
申请人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
发明人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
IPC分类号： G06F11/00 , G09G5/06 , G09G5/18 , G09G1/28
CPC分类号： G06F11/006 , G09G5/06 , G09G5/18
摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.
摘要翻译：响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。电路响应于消隐数据选择性地启用和禁用移位时钟。响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。电路将彩色数据字选择性地写入这些多个位置。电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。

2. 依法登记的发明

USH1690H Process for bleaching kraft pulp 失效
标题翻译：漂白牛皮纸浆的方法
公开(公告)号：USH1690H
公开(公告)日：1997-11-04
申请号：US504818
申请日：1995-07-20
申请人： Jeffrey Nye
发明人： Jeffrey Nye
IPC分类号： D21C9/10 , D21C3/20
CPC分类号： D21C9/1084 , D21C9/1042 , D21C9/1057
摘要： A method for bleaching lignocellulose containing pulp which has been chemically pulped is described wherein the method comprises the steps of sequentially treating the pulp with a reducing agent, a chelating agent and an oxidative agent.
摘要翻译：描述了一种用于漂白已经化学制浆的含木素纤维素的纸浆的方法，其中所述方法包括用还原剂，螯合剂和氧化剂依次处理纸浆的步骤。

3. 发明授权

US5607547A Method for reduced sulfur dioxide formation in refiner bleaching 失效
标题翻译：在精炼机漂白中减少二氧化硫形成的方法
公开(公告)号：US5607547A
公开(公告)日：1997-03-04
申请号：US445318
申请日：1995-05-19
申请人： Jeffrey Nye , Martin G. Fairbank
发明人： Jeffrey Nye , Martin G. Fairbank
IPC分类号： D21B1/16 , D21C9/10 , D21C9/12
CPC分类号： D21C9/1089 , D21B1/16
摘要： A method for eliminating the formation of sulfur dioxide in a refiner bleaching process is disclosed wherein a selected amount of a carbonate is added to the refiner contents at approximately the same time that sodium dithionite is added.
摘要翻译：公开了一种在精制漂白方法中消除二氧化硫形成的方法，其中在加入连二亚硫酸钠的大约相同的时间内将选定量的碳酸酯加入到精制机内容物中。

4. 发明申请

US20060179186A1 Method and apparatus for adaptive buffer sizing 有权
标题翻译：自适应缓冲区大小的方法和装置
公开(公告)号：US20060179186A1
公开(公告)日：2006-08-10
申请号：US11047410
申请日：2005-01-31
申请人： Jeffrey Nye , Sam Sandbote
发明人： Jeffrey Nye , Sam Sandbote
IPC分类号： G06F5/00
CPC分类号： G06F5/06 , G06F2205/063
摘要： A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.
摘要翻译：用于自适应缓冲器大小的方法和装置在不同的系统条件下，使用“高水位”到不同的级别来调整不同级别的缓冲器的大小。缓冲区逻辑使用高水位标记作为何时断言缓冲区“满”标志的指示。反过来，指令提取逻辑使用完整标志作为何时停止提取进一步指令的指示。

5. 发明申请

US20060095750A1 Processes, circuits, devices, and systems for branch prediction and other processor improvements 有权
标题翻译：用于分支预测和其他处理器改进的过程，电路，设备和系统
公开(公告)号：US20060095750A1
公开(公告)日：2006-05-04
申请号：US11210354
申请日：2005-08-24
申请人： Jeffrey Nye , Thang Tran
发明人： Jeffrey Nye , Thang Tran
IPC分类号： G06F9/44
CPC分类号： G06F9/3848
摘要： A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140) associated with said fetch stage (1710) and operable to store a pattern of predicted branches, said second storing circuit (wGHR 2140) coupled to said first storing circuit (aGHR 2130), said execute stage (1870) coupled back to said first storing circuit (aGHR 2130). Other processors, wireless communications devices, systems, circuits, devices, branch prediction processes and methods of operation, processes of manufacture, and articles of manufacture, as disclosed and claimed.
摘要翻译：用于处理指令的处理器（1700）具有包括提取级（1710）和执行级（1870）的流水线（1710,1736,1740），与所述读取级（1710）相关联的第一存储电路（aGHR 2130）和可操作地存储实际分支的历史，以及与所述提取级（1710）相关联的第二存储电路（wGHR 2140），并且可操作以存储预测分支的模式，所述第二存储电路（wGHR 2140）耦合到所述第一存储电路（aGHR 2130），所述执行级（1870）耦合回所述第一存储电路（aGHR 2130）。公开和要求保护的其它处理器，无线通信设备，系统，电路，设备，分支预测过程和操作方法，制造过程和制品。

6. 发明申请

US20060064551A1 Cache lock mechanism with speculative allocation 有权
公开(公告)号：US20060064551A1
公开(公告)日：2006-03-23
申请号：US11215684
申请日：2005-08-29
申请人： Edwin Sutanto , Hoichi Cheong , Zhongru Lin , Jeffrey Nye
发明人： Edwin Sutanto , Hoichi Cheong , Zhongru Lin , Jeffrey Nye
IPC分类号： G06F12/00
CPC分类号： G06F12/0802
摘要： A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.

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