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1. 发明申请

US20080258234A1 SEMICONDUCTOR STRUCTURE FOR LOW PARASITIC GATE CAPACITANCE 有权
标题翻译：低隔离栅电容的半导体结构
公开(公告)号：US20080258234A1
公开(公告)日：2008-10-23
申请号：US11738666
申请日：2007-04-23
申请人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
发明人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
IPC分类号： H01L21/285 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/76814 , H01L21/7682 , H01L21/76832 , H01L21/76844 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
摘要翻译：半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平。由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

2. 发明授权

US07709910B2 Semiconductor structure for low parasitic gate capacitance 有权
标题翻译：用于低寄生栅极电容的半导体结构
公开(公告)号：US07709910B2
公开(公告)日：2010-05-04
申请号：US11738666
申请日：2007-04-23
申请人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
发明人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/76814 , H01L21/7682 , H01L21/76832 , H01L21/76844 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
摘要翻译：半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平。由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

3. 发明授权

US07615418B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07615418B2
公开(公告)日：2009-11-10
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

4. 发明授权

US07791144B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07791144B2
公开(公告)日：2010-09-07
申请号：US12506770
申请日：2009-07-21
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及一种制造半导体结构和方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极中的应力诱导材料以及PFET和NFET沟道的变化的厚度。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

5. 发明申请

US20100013024A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20100013024A1
公开(公告)日：2010-01-21
申请号：US12506770
申请日：2009-07-21
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

6. 发明授权

US07608489B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07608489B2
公开(公告)日：2009-10-27
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

7. 发明授权

US08803243B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US08803243B2
公开(公告)日：2014-08-12
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

8. 发明申请

US20130168776A1 Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor 有权
标题翻译：互补金属氧化物半导体（CMOS）器件，其栅极结构由金属栅极导体连接
公开(公告)号：US20130168776A1
公开(公告)日：2013-07-04
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

9. 发明授权

US07675118B2 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration 失效
标题翻译：使用简化的双重应力衬垫配置提高性能的半导体结构
公开(公告)号：US07675118B2
公开(公告)日：2010-03-09
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

10. 发明授权

US07485519B2 After gate fabrication of field effect transistor having tensile and compressive regions 失效
标题翻译：栅极制造具有拉伸和压缩区域的场效应晶体管
公开(公告)号：US07485519B2
公开(公告)日：2009-02-03
申请号：US11693786
申请日：2007-03-30
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/66628 , H01L21/84 , H01L29/1083 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.
摘要翻译：形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包括应力。形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

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