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    • 4. 发明授权
    • Two-stage auto-zero amplifier circuit for electro-optical arrays
    • 用于电光阵列的两级自动归零放大器电路
    • US06803555B1
    • 2004-10-12
    • US09949320
    • 2001-09-07
    • William J. ParrishNaseem Y. Aziz
    • William J. ParrishNaseem Y. Aziz
    • H01J4014
    • G01J1/46G01J2001/444
    • Two-stage auto-zero amplifier circuits are disclosed, along with methods of auto-zeroing such amplifier circuits. The two-stage auto-zero amplifier circuit may be part of an electronics signal chain coupled to a detector element to process an electronic signal induced by illumination. In an exemplary embodiment, the auto-zero amplifier circuit includes a first stage, which includes a low-noise fixed gain amplifier, capacitively coupled to a second stage, which includes a high gain amplifier. In an exemplary embodiment of a method of auto-zeroing the two-stage auto-zero amplifier circuit, a first terminal of the detector element is decoupled from the auto-zero amplifier circuit, and the first stage of the auto-zero amplifier circuit is locally referenced to a second terminal of the detector element. An auto-zero voltage for the auto-zero amplifier circuit is stored between the first stage of the auto-zero amplifier circuit and the second stage of the auto-zero amplifier circuit.
    • 公开了两级自动归零放大器电路,以及自动归零这种放大器电路的方法。 两级自动归零放大器电路可以是耦合到检测器元件的电子信号链的一部分,以处理由照明引起的电子信号。 在示例性实施例中,自动调零放大器电路包括第一级,其包括电容耦合到第二级的低噪声固定增益放大器,其包括高增益放大器。 在自动归零两级自动归零放大器电路的方法的示例性实施例中,检测器元件的第一端子与自动调零放大器电路去耦,自动调零放大器电路的第一级为 局部地参考检测器元件的第二端子。 自动归零放大器电路的自动归零电压存储在自动归零放大器电路的第一级和自动归零放大器电路的第二级之间。
    • 5. 发明授权
    • Differential current mode output circuit for electro-optical sensor arrays
    • 差分电流模式输出电路用于电光传感器阵列
    • US06344651B1
    • 2002-02-05
    • US09427645
    • 1999-10-27
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • H03F345
    • G01J5/24H03F3/082H03F3/45197H03F3/68H03F2203/45652H03F2203/45658H03F2203/45682H04N5/33
    • A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node. The current flow through Rs is proportional to a difference between Vs and Vr, and is thus indicative of a magnitude of Vs.
    • 差分电流模式放大器电路(5,5')包括具有第一电流源的第一电路支路,该第一电流源提供与第一电路节点(n1)上的第一晶体管(m1)串联耦合的电流I1。 第一晶体管具有用于耦合到输入信号电位(Vs)的控制端子。 Vs是从放射线检测器阵列的单位单元获得的,并且表示积分的光子诱导电荷的大小。 第一电路支路输出第一输出电流(Is)。 第二电路支路包括提供与第二电路节点(n2)上的第二晶体管(m2)串联耦合的电流I2的第二电流源。 第二晶体管具有用于耦合到输入参考电位(Vr)的控制端子。 第二电路支路输出第二输出电流(Ir)。 电阻(Rs)在第一电路节点和第二节点处耦合在第一电路支路和第二电路支路之间。 通过Rs的电流与Vs和Vr之间的差成比例,因此表示Vs的大小。
    • 8. 发明授权
    • Constant power snapshot microemitter array with integral digital interface, isolated substrate current return, and linearized signal response
    • 具有集成数字接口的恒功率快照微阵列阵列,隔离衬底电流返回和线性化信号响应
    • US06316777B1
    • 2001-11-13
    • US09285509
    • 1999-04-02
    • William J. ParrishNaseem Y. AzizJeffrey L. HeathTheodore R. Hoelter
    • William J. ParrishNaseem Y. AzizJeffrey L. HeathTheodore R. Hoelter
    • G01J100
    • H01L27/16H04N5/33H04N5/3651
    • A dual sample-and-hold architecture in each unit cell of a read-in-integrated-circuit (RIIC) provides maximum frame rate without frame overlap. Analog pixel signals are updated sequentially in one sample-and-hold capacitor, while an emitter element displays a pixel of a display frame in response to a stored analog signal voltage on an isolated second sample-and-hold capacitor. After all unit cells are updated, the signals on the two capacitors are combined, updating all emitter elements for the next frame. A voltage mode amplifier as an emitter driver provides a more nearly linear dependence of infrared power output on signal voltage than do previous transconductance amplifiers. A digital to analog converter (DAC) on the RIIC substrate results in a simplified interface to the RIIC and in an increased immunity to noise. A constant current source in the unit cell provides constant power dissipation and temperature, independent from variations in emitter element current, improving stability and scene dependent crosstalk. Emitter element current returns to an external ground plane through semiconductor substrate contacts for all unit cells. This configuration eliminates metal interconnects, which produce scene-dependent voltage drops in the return circuit, adversely affecting linearity and crosstalk.
    • 在集成电路(RIIC)的每个单元中的双采样保持架构提供了最大的帧速率,而没有帧重叠。 模拟像素信号在一个采样和保持电容器中顺序更新,而发射极元件响应于隔离的第二采样保持电容器上存储的模拟信号电压而显示显示帧的像素。 在更新了所有单元电池之后,两个电容器上的信号被组合,更新下一帧的所有发射极元件。 作为发射极驱动器的电压模式放大器比以前的跨导放大器提供了更接近于线性的信号电压对信号电压的依赖性。 RIIC衬底上的数模转换器(DAC)可实现对RIIC的简化接口,并增加对噪声的抗扰度。 单元电池中的恒流源提供恒定的功耗和温度,独立于发射极元件电流的变化,提高稳定性和场景相关串扰。 发射极元件电流通过半导体衬底触点返回到外部接地层,用于所有单元电池。 该配置消除了在返回电路中产生场景相关电压降的金属互连,不利地影响线性度和串扰。
    • 9. 发明授权
    • Methods and circuitry for correcting temperature-induced errors in
microbolometer focal plane array
    • 用于校正微测辐射计焦平面阵列温度导致误差的方法和电路
    • US6028309A
    • 2000-02-22
    • US021714
    • 1998-02-10
    • William J. ParrishJames T. Woolaway
    • William J. ParrishJames T. Woolaway
    • G01J5/20G01J5/22H04N5/33H04N5/365G01J5/24
    • H04N5/33G01J5/20G01J5/22H04N5/3651
    • Correction for temperature-induced non-uniformities in the response characteristics of the microbolometers in an infrared focal plane array (FPA) is performed by applying a non-uniform corrective bias to the individual microbolometers. The corrective bias is applied either before or during the bias or integration period during which the detectors are sampled. The bias-correction can be applied to two-dimensional detector multiplexers at each column amplifier input, the reference potential for each column amplifier or the voltage supply for each detector element. The magnitude of each corrective bias is determined by calibrating the detectors at different temperatures and different levels of incident infrared radiation. According to another aspect of this invention, a microbolometer which is thermally-shorted to the substrate on which the read out integrated circuit (ROIC) is formed is used along with the sensing microbolometer to compensate for variations in temperature. In some embodiments, an adjustable voltage is applied to the thermally-shorted microbolometer to provide an offset correction. Circuitry for providing on-ROIC substrate temperature control is also described. This invention allows the operation of a microbolometer FPA over a wider range of device substrate temperatures and thereby significantly reduces the complexity and cost of the system as compared with the conventional technique of cooling the FPA.
    • 红外焦平面阵列(FPA)中的微量热计的响应特性中的温度诱导的不均匀性的校正是通过对各个微量热计进行不均匀的校正偏差来进行的。 纠正偏压在采样检测器的偏置或积分期间之前或期间施加。 偏置校正可以应用于每个列放大器输入处的二维检测器多路复用器,每个列放大器的参考电位或每个检测器元件的电压源。 每个校正偏差的大小通过校准不同温度和不同入射红外辐射水平的检测器来确定。 根据本发明的另一方面,与传感微电热计一起使用热短路至其上形成读出的集成电路(ROIC)的衬底的微热辐射计,以补偿温度变化。 在一些实施例中,将可调节的电压施加到热短路微电热计上以提供偏移校正。 还描述了用于提供ROIC衬底温度控制的电路。 与传统的冷却FPA技术相比,本发明允许在更宽范围的器件衬底温度下操作微热辐射计FPA,从而显着降低系统的复杂性和成本。
    • 10. 发明授权
    • Wafer scale testing of redundant integrated circuit dies
    • 冗余集成电路芯片的晶圆尺度测试
    • US4956602A
    • 1990-09-11
    • US310841
    • 1989-02-14
    • William J. Parrish
    • William J. Parrish
    • G01R31/28G01R31/317G01R31/3185G06F11/22G06F11/26G11C29/00H01L21/66
    • H01L22/22G01R31/2831G01R31/31712G01R31/31715G01R31/318505G01R31/318511G06F11/26G11C29/006G06F11/2273H01L2924/0002
    • A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuuit dies should shorting occur during dicing. The integrated circuit dies and wafer scale test system may optionally be partitioned into several separate groups to prevent faults in the interchip multiplexor system from rendering the entire wafer useless.
    • 用于测试形成在半导体晶片上的冗余集成电路管芯的晶片级测试系统包括形成在晶片上的晶片级测试焊盘和用于将施加到晶片尺度测试焊盘的测试信号引导到各个集成电路管芯的芯片间复用器装置。 芯片间复用器装置包括用于接收来自晶片焊盘的测试信号的输入/输出缓冲电路,并将测试信号施加到被路由到各个电路管芯的选定的芯片间多路复用器线路。 所述集成电路管芯上的输出焊盘的读出通过输入/输出缓冲电路返回到晶片测试焊盘,以提供测试输出信号。 在集成电路裸片接触焊盘和芯片间复用器线之间的切割通道之间提供低横截面连接装置,以避免在切割操作期间的短路。 此外,提供线路保护电路以防止在切割期间发生短路时的集成循环模具的破坏。 集成电路管芯和晶片刻度测试系统可以可选地分成几个单独的组,以防止芯片间复用器系统中的故障使整个晶片无用。