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1. 发明授权

US07130231B2 Method, apparatus, and computer program product for implementing enhanced DRAM interface checking 失效
标题翻译：用于实现增强型DRAM接口检查的方法，装置和计算机程序产品
公开(公告)号：US07130231B2
公开(公告)日：2006-10-31
申请号：US10994087
申请日：2004-11-19
申请人： William Hugh Cochran , William Paul Hovis
发明人： William Hugh Cochran , William Paul Hovis
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C11/401 , G11C29/18
摘要： A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are checked for a proper value being applied and an error is signaled for unexpected results. An extended test mode includes further testing during a cycle after the refresh command cycle. Then command inputs also are checked for a proper value being applied and an error is signaled for unexpected results.
摘要翻译：提供了一种用于实现增强的DRAM接口检查的方法，装置和计算机程序产品。接口检查模式使用DRAM的刷新命令进行接口检查。在刷新命令循环期间为接口地址输入提供预定义的地址模式。检查接口地址输入是否正在应用值，并发出错误信号，以获取意外结果。扩展测试模式包括在刷新命令周期之后的一个周期内的进一步测试。然后，还将检查命令输入是否正在应用值，并发出错误信号，以获得意外结果。

2. 发明授权

US07603528B2 Memory device verification of multiple write operations 失效
标题翻译：多个写入操作的内存设备验证
公开(公告)号：US07603528B2
公开(公告)日：2009-10-13
申请号：US10961745
申请日：2004-10-08
申请人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
发明人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F12/0804 , G06F12/084
摘要： Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.
摘要翻译：利用验证操作来有效地验证多个关联的写入操作。可以在发出数据到存储器存储设备的多个写入操作的发出之后启动验证操作，并且可以被配置为仅通过多个写入验证写入存储器存储设备的数据的子集操作。结果，在每次写入操作之后不需要执行验证操作，因此可以显着减少验证操作的数量，从而可以大大减少由此消耗的处理和通信带宽。

3. 发明授权

US07225375B2 Method and apparatus for detecting array degradation and logic degradation 有权
标题翻译：用于检测阵列退化和逻辑劣化的方法和装置
公开(公告)号：US07225375B2
公开(公告)日：2007-05-29
申请号：US10815248
申请日：2004-03-31
申请人： William Hugh Cochran , William Paul Hovis
发明人： William Hugh Cochran , William Paul Hovis
IPC分类号： G01R31/28
CPC分类号： G11C29/50012 , G01R31/318516 , G11C29/14 , G11C29/50 , G11C2029/5004
摘要： A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine coupled to at least one monitor element that is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.
摘要翻译：提供了一种用于在包括专用集成电路（ASIC））的集成电路（IC）中检测诸如阵列劣化和逻辑劣化的劣化的方法和装置。耦合到由集成电路中的预定义电路元件定义的至少一个监视器元件的监视器内置自检（MBIST）引擎。 MBIST引擎用于控制至少一个监视元件的操作，用于与监视位进行通信，以识别信号的劣化，定时和电压裕度。

4. 发明授权

US07228484B2 Method and apparatus for implementing redundancy enhanced differential signal interface 有权
标题翻译：实现冗余增强差分信号接口的方法和装置
公开(公告)号：US07228484B2
公开(公告)日：2007-06-05
申请号：US10660032
申请日：2003-09-11
申请人： William Hugh Cochran , William Paul Hovis , Randall Scott Jensen
发明人： William Hugh Cochran , William Paul Hovis , Randall Scott Jensen
IPC分类号： H03M13/00
CPC分类号： G01R31/31715
摘要： A method and apparatus are provided for implementing a redundancy enhanced differential signal interface. A differential signaling I/O pair is coupled to a differential receiver interface. The differential receiver interface includes a pair of multiplexers coupled to a differential receiver. An error detecting mechanism is coupled to the differential receiver for detecting an error. When an error is detected, an interface operating speed is reduced. True and complement sides of a differential signaling I/O pair are alternately tested by first enabling a multiplexer control of one of the multiplexers, reading data, and checking for the error; then enabling a multiplexer control of the other multiplexer, reading data, and checking for the error. Responsive to detecting a failure of a true side or a complement side, the detected failed true side or complement side is set to a reference voltage and the reduced interface operating speed is maintained for continued operation.
摘要翻译：提供了一种用于实现冗余增强的差分信号接口的方法和装置。差分信号I / O对耦合到差分接收器接口。差分接收器接口包括耦合到差分接收器的一对多路复用器。误差检测机构耦合到差分接收器，用于检测误差。当检测到错误时，界面操作速度降低。通过首先启用多路复用器之一的多路复用器控制，读取数据和检查错误来交替测试差分信号I / O对的真和补码侧; 然后启用另一个多路复用器的多路复用器控制，读取数据和检查错误。响应于检测真实侧或补偿侧的故障，检测到的失败的真实侧或补偿侧被设置为参考电压，并且维持降低的接口操作速度以继续操作。

5. 发明授权

US07185246B2 Monitoring of solid state memory devices in active memory system utilizing redundant devices 有权
标题翻译：使用冗余设备监控活动存储器系统中的固态存储器件
公开(公告)号：US07185246B2
公开(公告)日：2007-02-27
申请号：US11013150
申请日：2004-12-15
申请人： William Hugh Cochran , William Paul Hovis
发明人： William Hugh Cochran , William Paul Hovis
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G11C29/806 , G11C2029/0409
摘要： Redundant capacity in a memory system is utilized to facilitate active monitoring of solid state memory devices in the memory system. All or part of the data stored in an active solid state memory device, and used in an active data processing system, may be copied to at least one redundant memory device, e.g., by transitioning a memory address range that was allocated to the active memory device to the redundant memory device. By doing so, memory access requests for the memory address range, which would normally be directed to the active memory device, may instead be directed to the redundant memory device, thus enabling the active memory device to be tested (e.g., via writing and reading test data patterns to the active memory device) without interrupting system access to that memory address range.
摘要翻译：利用存储器系统中的冗余容量来促进对存储器系统中的固态存储器件的主动监视。存储在活动固态存储设备中并在活动数据处理系统中使用的数据的全部或部分数据可被复制到至少一个冗余存储器设备，例如通过转换分配给活动存储器的存储器地址范围设备到冗余存储设备。通过这样做，存储器地址范围的存储器访问请求通常被定向到活动存储器设备，可以被引导到冗余存储器设备，从而使活动存储器件能够被测试（例如，通过写入和读取测试数据模式到活动存储设备），而不会中断对该存储器地址范围的系统访问。

6. 发明授权

US07309911B2 Method and stacked memory structure for implementing enhanced cooling of memory devices 有权
标题翻译：用于实现存储器件的增强冷却的方法和堆叠存储器结构
公开(公告)号：US07309911B2
公开(公告)日：2007-12-18
申请号：US11138939
申请日：2005-05-26
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Hugh Cochran , William Paul Hovis , Paul Rudrud
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Hugh Cochran , William Paul Hovis , Paul Rudrud
IPC分类号： H01L23/495
CPC分类号： H01L25/105 , H01L25/18 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H01L2924/1627 , H01L2924/00
摘要： A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.
摘要翻译：提供了一种用于实现多个存储器件的增强冷却的方法和结构。存储器结构包括堆叠的盘片。每个盘片上安装有多个存储器件。至少一个连接器设置有每个盘片，用于连接到子多个存储器件。散热器与用于冷却多个存储器件的盘堆相关联。

7. 发明授权

US07032056B2 Encoding of message onto strobe signals 有权
标题翻译：消息编码到选通信号
公开(公告)号：US07032056B2
公开(公告)日：2006-04-18
申请号：US10431928
申请日：2003-05-08
申请人： William Hugh Cochran , William Paul Hovis
发明人： William Hugh Cochran , William Paul Hovis
IPC分类号： H03M13/00 , G06F11/00 , G06F13/38
CPC分类号： G06F13/4273 , Y10S370/912
摘要： Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when, in a window of time, the receiving electronic component should latch the data. In many such systems, data is transmitted over the signaling conductors in the form of a plurality “beats”, of data, proper timing to latch each beat of data being identified by a transition of the strobe signal. Faults in components or errors in transmission must be handled. The present invention discloses apparatus and methods to communicate conditions relevant to data transmitted without requiring additional signaling conductors. The present invention discloses selecting a message from a plurality of messages, encoding the selected message, and transmitting the encoded message on existing strobe lines to communicate the condition encountered.
摘要翻译：公开了用于电子系统中的方法和装置，其中使用伴随数据的选通信号，通过信令导体从一个电子部件传输数据。选通信号的边沿或转换标识何时在时间窗口中接收电子部件应该锁存数据。在许多这样的系统中，数据通过信号导体以多个“节拍”的形式传输，数据的适当定时，以锁存通过选通信号的转换来识别的数据的每个节拍。必须处理组件故障或传输错误。本发明公开了用于传送与传送的数据有关的条件的装置和方法，而不需要额外的信令导体。本发明公开了从多个消息中选择消息，编码所选择的消息，以及在现有频闪线上发送编码消息以传达所遇到的状况。

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