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1. 发明授权

US06563183B1 Gate array with multiple dielectric properties and method for forming same 失效
标题翻译：具有多种介电特性的门阵列及其形成方法
公开(公告)号：US06563183B1
公开(公告)日：2003-05-13
申请号：US10085949
申请日：2002-02-28
申请人： William G. En , Arvind Halliyal , Minh-Ren Lin , Minh Van Ngo , Cyrus E. Tabery , Chih-Yuh Yang
发明人： William G. En , Arvind Halliyal , Minh-Ren Lin , Minh Van Ngo , Cyrus E. Tabery , Chih-Yuh Yang
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823462
摘要： The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant. The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant. The first dielectric constant and the second dielectric constant may be different and both may be greater than the dielectric constant of silicon dioxide.
摘要翻译：本发明提供一种在半导体衬底上制造的集成电路。集成电路包括第一场效应晶体管和第二场效应晶体管。第一场效应晶体管包括位于衬底的第一沟道区上方的第一多晶硅栅极，并通过延伸第一多晶硅栅极的整个长度的第一电介质层与第一沟道区隔离。第一电介质层包括具有第一介电常数的第一电介质材料。第二场效应晶体管包括位于衬底上的第二沟道区上方的第二多晶硅栅极，并且通过延伸第二多晶硅栅极的整个长度的第二电介质层与第二沟道区隔离。第二电介质层包括具有第二介电常数的第二电介质材料。第一介电常数和第二介电常数可以是不同的，并且它们都可以大于二氧化硅的介电常数。

2. 发明授权

US06599766B1 Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer 有权
标题翻译：确定用于图案化薄膜半导体层的抗反射涂层厚度的方法
公开(公告)号：US06599766B1
公开(公告)日：2003-07-29
申请号：US10093596
申请日：2002-03-08
申请人： Cyrus E. Tabery , Chih-Yuh Yang , Minh Van Ngo
发明人： Cyrus E. Tabery , Chih-Yuh Yang , Minh Van Ngo
IPC分类号： H01L2100
CPC分类号： G03F7/091 , G02B1/115
摘要： The invention provides a method of selecting an anti reflective layer thickness for patterning a thin film silicon gate layer over a high K dielectric layer. The method comprises selecting a trial anti reflective layer thickness. A first coherent illumination intensity reflected from an interface between the photoresist layer and the anti reflective layer is calculated at the lithography wavelength. A second coherent illumination intensity reflected from an interface between the anti reflective layer and the polysilicon layer is calculated at the lithography wavelength. And, a third coherent illumination intensity reflected from an interface between the polysilicon layer and the high K dielectric layer is calculated at the lithography wavelength. A total coherent illumination intensity that comprises the sum of the first coherent illumination intensity, the second coherent illumination intensity, and the third coherent illumination intensity is calculated and compared to a predetermined threshold. If below the threshold, the trail anti reflective layer thickness is selected as the anti reflective layer thickness.
摘要翻译：本发明提供一种选择抗反射层厚度以在高K电介质层上图案化薄膜硅栅极层的方法。该方法包括选择试验抗反射层厚度。在光刻波长处计算从光致抗蚀剂层和抗反射层之间的界面反射的第一相干照明强度。在光刻波长处计算从抗反射层和多晶硅层之间的界面反射的第二相干照明强度。并且，在光刻波长处计算从多晶硅层和高K电介质层之间的界面反射的第三相干照明强度。计算包括第一相干照明强度，第二相干照射强度和第三相干照明强度的总和的总相干照明强度并将其与预定阈值进行比较。如果低于阈值，则选择防反射层厚度作为抗反射层厚度。

3. 发明授权

US06787476B1 Etch stop layer for etching FinFET gate over a large topography 有权
标题翻译：蚀刻停止层，用于在大地形上蚀刻FinFET栅极
公开(公告)号：US06787476B1
公开(公告)日：2004-09-07
申请号：US10632989
申请日：2003-08-04
申请人： Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Chih-Yuh Yang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21302
CPC分类号： H01L29/785 , H01L21/31116 , H01L21/31144 , H01L29/4908 , H01L29/66795
摘要： A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.
摘要翻译：提供了一种形成Fin场效应晶体管（FinFET）的栅极的方法。该方法包括在翅片上形成第一层材料，并在第一层上形成第二层。第二层包括Ti或TiN。该方法还包括在第二层上形成第三层。第三层包括抗反射涂层。该方法还包括蚀刻第一，第二和第三层以形成用于FinFET的栅极。

4. 发明授权

US07029959B1 Source and drain protection and stringer-free gate formation in semiconductor devices 有权
标题翻译：半导体器件中的源极和漏极保护和无栅极栅极形成
公开(公告)号：US07029959B1
公开(公告)日：2006-04-18
申请号：US10429737
申请日：2003-05-06
申请人： Chih-Yuh Yang , Shibly S. Ahmed , Srikanteswara Dakshina-Murhty , Cyrus E. Tabery , Bin Yu
发明人： Chih-Yuh Yang , Shibly S. Ahmed , Srikanteswara Dakshina-Murhty , Cyrus E. Tabery , Bin Yu
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.
摘要翻译：制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。该方法还可以包括在栅极材料上沉积有机抗反射涂层并在有机抗反射涂层上形成栅极掩模。可以去除栅极掩模周围的有机抗反射涂层，并且可以去除栅极掩模周围的栅极材料以限定栅极。

5. 发明授权

US07029958B2 Self aligned damascene gate 有权
标题翻译：自对准镶嵌门
公开(公告)号：US07029958B2
公开(公告)日：2006-04-18
申请号：US10699887
申请日：2003-11-04
申请人： Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模。该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和漏极区域。

6. 发明授权

US06787854B1 Method for forming a fin in a finFET device 有权
标题翻译：在finFET器件中形成翅片的方法
公开(公告)号：US06787854B1
公开(公告)日：2004-09-07
申请号：US10385753
申请日：2003-03-12
申请人： Chih-Yuh Yang , Shibly S. Ahmed , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Bin Yu
发明人： Chih-Yuh Yang , Shibly S. Ahmed , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Bin Yu
IPC分类号： H01L218238
CPC分类号： H01L29/7853 , H01L29/66818
摘要： A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.
摘要翻译：一种在绝缘体上硅（SOI）晶片上形成翅片结构的方法，包括在半导体衬底上形成的绝缘层上的硅层，包括使用第一蚀刻步骤蚀刻硅层，然后蚀刻第一蚀刻步骤，使用第二蚀刻步骤的硅层，以及在第二蚀刻程序之后，使用第三蚀刻工艺蚀刻硅层以形成T形翅片结构。

7. 发明授权

US07915160B1 Methods for forming small contacts 有权
标题翻译：形成小触点的方法
公开(公告)号：US07915160B1
公开(公告)日：2011-03-29
申请号：US11625190
申请日：2007-01-19
申请人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.
摘要翻译：提供了用于形成用于半导体器件的触点的方法。所述方法可以包括在半导体器件上沉积诸如多晶硅，氮化物，氧化物和/或碳材料的各种材料。所述方法还可以包括形成接触孔并填充接触孔以形成用于半导体器件的接触。

8. 发明授权

US07183223B1 Methods for forming small contacts 有权
标题翻译：形成小触点的方法
公开(公告)号：US07183223B1
公开(公告)日：2007-02-27
申请号：US10728909
申请日：2003-12-08
申请人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.
摘要翻译：提供了用于形成用于半导体器件的触点的方法。所述方法可以包括在半导体器件上沉积诸如多晶硅，氮化物，氧化物和/或碳材料的各种材料。所述方法还可以包括形成接触孔并填充接触孔以形成用于半导体器件的接触。

9. 发明授权

US06790782B1 Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal 有权
标题翻译：包括高K栅极电介质的晶体管栅极的制造工艺，其具有原位抗蚀剂修整，栅极蚀刻和高K电介质去除
公开(公告)号：US06790782B1
公开(公告)日：2004-09-14
申请号：US10157450
申请日：2002-05-29
申请人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
发明人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
IPC分类号： H01L21302
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/28273 , H01L29/517
摘要： The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.
摘要翻译：本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。在高K电介质层上方制造多晶硅层。在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

10. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

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