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1. 发明授权

US07191305B2 Method and apparatus for address decoding of embedded DRAM devices 有权
标题翻译：嵌入式DRAM器件的地址解码方法和装置
公开(公告)号：US07191305B2
公开(公告)日：2007-03-13
申请号：US10952269
申请日：2004-09-28
申请人： William D. Corti , Joseph O. Marsh , Michael Won
发明人： William D. Corti , Joseph O. Marsh , Michael Won
IPC分类号： G06F12/00
CPC分类号： G11C8/04
摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
摘要翻译：公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。随后，一组初始列地址位在稍后的时间从存储器管理器。初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。

2. 发明授权

US06834360B2 On-chip logic analyzer 有权
标题翻译：片上逻辑分析仪
公开(公告)号：US06834360B2
公开(公告)日：2004-12-21
申请号：US09683091
申请日：2001-11-16
申请人： William D. Corti , Robert Kenny, Jr. , Joseph O. Marsh , Steven C. Parker , Frank X. Scanzano , Michael Won
发明人： William D. Corti , Robert Kenny, Jr. , Joseph O. Marsh , Steven C. Parker , Frank X. Scanzano , Michael Won
IPC分类号： G06F1100
CPC分类号： G06F11/3648 , G06F11/3636
摘要： An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.
摘要翻译：片上逻辑分析（OCLA）系统捕获由嵌入在单芯片器件（SOC）中的信号处理逻辑核处理的数据，而不中断信号处理逻辑核的操作。 OCLA系统包括嵌入在SOC装置中的数据捕获单元，用于监视信号处理单元的操作，并确定操作是否满足预定的触发条件。一旦满足触发条件，数据捕获单元从信号处理单元捕获内部数据并将其传送到外部主机系统。主机系统控制数据采集单元的操作。主机系统将捕获的数据提供给用户界面，用于测试和调试SOC信号处理设备的操作。

3. 发明授权

US06834334B2 Method and apparatus for address decoding of embedded DRAM devices 失效
标题翻译：嵌入式DRAM器件的地址解码方法和装置
公开(公告)号：US06834334B2
公开(公告)日：2004-12-21
申请号：US09940262
申请日：2001-08-28
申请人： William D. Corti , Joseph O. Marsh , Michael Won
发明人： William D. Corti , Joseph O. Marsh , Michael Won
IPC分类号： G06F1200
CPC分类号： G11C8/04
摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
摘要翻译：公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。随后，一组初始列地址位在稍后的时间从存储器管理器。初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。

4. 发明申请

US20130069688A1 DIGITAL TEST SYSTEM AND METHOD FOR VALUE BASED DATA 失效
标题翻译：数字测试系统和价值数据的方法
公开(公告)号：US20130069688A1
公开(公告)日：2013-03-21
申请号：US13233374
申请日：2011-09-15
申请人： Eugene Rogers Atwood , Thomas Joseph Bardsley , Victor Moy , Michael Won
发明人： Eugene Rogers Atwood , Thomas Joseph Bardsley , Victor Moy , Michael Won
IPC分类号： H03K19/00
CPC分类号： H03K19/096
摘要： Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.
摘要翻译：本发明的实施例提供了一种不等式指示系统（IIS）。 IIS提供了内置的测试支持，可以在片上数字逻辑电路中将数字值作为不等式进行评估，在设备I / O上表示单个通过/失败位或包含不等式评估结果的可读寄存器。 IIS使用通用简单的方法将值评估移动到设备（芯片）上，非常适合地址/数据类型结构或基于扫描的结构，而不是片外，然后需要依赖于测试者的自定义代码。 IIS启用时，会覆盖TDO信号，以使其能够用作不等式指示器，而不是标准测试数据输出信号。

5. 发明申请

US20050044337A1 Method and apparatus for address decoding of embedded DRAM devices 有权
标题翻译：嵌入式DRAM器件的地址解码方法和装置
公开(公告)号：US20050044337A1
公开(公告)日：2005-02-24
申请号：US10952269
申请日：2004-09-28
申请人： William Corti , Joseph Marsh , Michael Won
发明人： William Corti , Joseph Marsh , Michael Won
IPC分类号： G06F12/00 , G06F12/02 , G11C8/04
CPC分类号： G11C8/04
摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
摘要翻译：公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。随后，一组初始列地址位在稍后的时间从存储器管理器。初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。

6. 发明授权

US08405419B1 Digital test system and method for value based data 失效
标题翻译：数字测试系统和基于价值的数据的方法
公开(公告)号：US08405419B1
公开(公告)日：2013-03-26
申请号：US13233374
申请日：2011-09-15
申请人： Eugene Rogers Atwood , Thomas Joseph Bardsley , Victor Moy , Michael Won
发明人： Eugene Rogers Atwood , Thomas Joseph Bardsley , Victor Moy , Michael Won
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K19/096
摘要： Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.
摘要翻译：本发明的实施例提供了一种不等式指示系统（IIS）。 IIS提供了内置的测试支持，可以在片上数字逻辑电路中将数字值作为不等式进行评估，在设备I / O上表示单个通过/失败位或包含不等式评估结果的可读寄存器。 IIS使用通用简单的方法将值评估移动到设备（芯片）上，非常适合地址/数据类型结构或基于扫描的结构，而不是片外，然后需要依赖于测试者的自定义代码。 IIS启用时，会覆盖TDO信号，以使其能够用作不等式指示器，而不是标准测试数据输出信号。

7. 发明申请

US20050017350A1 Thermal enhanced extended surface tape for integrated circuit heat dissipation 审中-公开
标题翻译：热增强扩展表面胶带，用于集成电路散热
公开(公告)号：US20050017350A1
公开(公告)日：2005-01-27
申请号：US10921752
申请日：2004-08-18
申请人： William Corti , David Long , Joseph Marsh , Francis Scanzano , Michael Won , Tsorng-Dih Yuan
发明人： William Corti , David Long , Joseph Marsh , Francis Scanzano , Michael Won , Tsorng-Dih Yuan
IPC分类号： H01L23/367 , H01L23/10
CPC分类号： H01L23/3672 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2224/0401
摘要： A thermal conductive tape article is provided which is adhered to the surface of an integrated circuit device to dissipate heat from the device. The thermal conductive tape article is preferably corrugated and may have a number of configurations providing an expanded surface area. The corrugated tape article may also have a metal strip bonded to one or both sides of the tape article to form a single-faced or double-faced corrugated tape article. The tape article is preferably made of copper or aluminum.
摘要翻译：提供了一种粘合到集成电路器件表面以散发来自器件的热量的导热带制品。导热带制品优选是波纹状的，并且可以具有提供扩展表面积的许多构造。波纹带制品还可以具有粘合到带制品的一侧或两侧的金属条，以形成单面或双面波纹带制品。带状物优选由铜或铝制成。

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