专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07996653B2 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07996653B2
公开(公告)日：2011-08-09
申请号：US12899979
申请日：2010-10-07
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F9/30
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

2. 发明授权

US07383423B1 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07383423B1
公开(公告)日：2008-06-03
申请号：US10957250
申请日：2004-10-01
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F15/00
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

3. 发明申请

US20110024800A1 Shared Resources in a Chip Multiprocessor 有权
标题翻译：芯片多处理器中的共享资源
公开(公告)号：US20110024800A1
公开(公告)日：2011-02-03
申请号：US12899979
申请日：2010-10-07
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： H01L23/52 , H01L21/326
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

4. 发明授权

US07840780B2 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07840780B2
公开(公告)日：2010-11-23
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F9/00
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

5. 发明申请

US20080184009A1 Shared Resources in a Chip Multiprocessor 有权
标题翻译：芯片多处理器中的共享资源
公开(公告)号：US20080184009A1
公开(公告)日：2008-07-31
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

6. 发明授权

US08195887B2 Processor power management and method 有权
标题翻译：处理器电源管理和方法
公开(公告)号：US08195887B2
公开(公告)日：2012-06-05
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

7. 发明申请

US20100185820A1 PROCESSOR POWER MANAGEMENT AND METHOD 有权
标题翻译：处理器功率管理和方法
公开(公告)号：US20100185820A1
公开(公告)日：2010-07-22
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

8. 发明申请

US20110301889A1 FLEXIBLE POWER REPORTING IN A COMPUTING SYSTEM 有权
标题翻译：计算机系统中的灵活电力报告
公开(公告)号：US20110301889A1
公开(公告)日：2011-12-08
申请号：US12792308
申请日：2010-06-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
发明人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
IPC分类号： G01R21/00 , G05D23/19 , G06F19/00
CPC分类号： G06F1/3203 , G06F1/206 , H05K7/20836 , Y02D10/16
摘要： A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on data corresponding to activity levels of one or more functional blocks within the processor. This data corresponds to each of a number of sampled signals within the one or more functional blocks rather than temperature. Thus, the data is independent of environment temperature variations. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent, such as a controller for a data center rack system. Responsive to receiving and processing the average power consumption number, the external agent may perform one or more actions. For example, the external agent may cause changes in a cooling system.
摘要翻译：一种有效报告电力使用的系统和方法。处理器内的电力报告单元从功率监视器接收每个采样间隔一次的功耗数字。功率监视器基于与处理器内的一个或多个功能块的活动级别对应的数据来确定功耗数量。该数据对应于一个或多个功能块内的多个采样信号中的每个，而不是温度。因此，数据与环境温度变化无关。基于运行时间间隔的接收功耗数来计算平均功耗数，其中运行时间间隔大于采样间隔。该值被传送到外部代理，例如用于数据中心机架系统的控制器。响应于接收和处理平均功耗数量，外部代理可以执行一个或多个动作。例如，外部代理可能导致冷却系统的变化。

9. 发明授权

US08442786B2 Flexible power reporting in a computing system 有权
标题翻译：计算系统中灵活的电力报告
公开(公告)号：US08442786B2
公开(公告)日：2013-05-14
申请号：US12792308
申请日：2010-06-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
发明人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
IPC分类号： G01R21/00 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , H05K7/20836 , Y02D10/16
摘要： A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on sampled signals within one or more functional blocks in the processor, rather than based on temperature. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent. Responsive to receiving and processing the average power consumption number, the external agent may cause changes in a cooling system.
摘要翻译：一种有效报告电力使用的系统和方法。处理器内的电力报告单元从功率监视器接收每个采样间隔一次的功耗数字。功率监视器基于处理器中的一个或多个功能块内的采样信号而不是基于温度来确定功耗数。基于运行时间间隔的接收功耗数来计算平均功耗数，其中运行时间间隔大于采样间隔。该值传送给外部代理。响应于接收和处理平均功耗数量，外部代理可能导致冷却系统的变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式