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1. 发明授权

US08195887B2 Processor power management and method 有权
标题翻译：处理器电源管理和方法
公开(公告)号：US08195887B2
公开(公告)日：2012-06-05
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

2. 发明申请

US20100185820A1 PROCESSOR POWER MANAGEMENT AND METHOD 有权
标题翻译：处理器功率管理和方法
公开(公告)号：US20100185820A1
公开(公告)日：2010-07-22
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

3. 发明申请

US20110024800A1 Shared Resources in a Chip Multiprocessor 有权
标题翻译：芯片多处理器中的共享资源
公开(公告)号：US20110024800A1
公开(公告)日：2011-02-03
申请号：US12899979
申请日：2010-10-07
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： H01L23/52 , H01L21/326
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

4. 发明授权

US07996653B2 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07996653B2
公开(公告)日：2011-08-09
申请号：US12899979
申请日：2010-10-07
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F9/30
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

5. 发明授权

US07383423B1 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07383423B1
公开(公告)日：2008-06-03
申请号：US10957250
申请日：2004-10-01
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F15/00
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

6. 发明授权

US07840780B2 Shared resources in a chip multiprocessor 有权
标题翻译：一个芯片多处理器共享资源
公开(公告)号：US07840780B2
公开(公告)日：2010-11-23
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F9/00
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

7. 发明申请

US20080184009A1 Shared Resources in a Chip Multiprocessor 有权
标题翻译：芯片多处理器中的共享资源
公开(公告)号：US20080184009A1
公开(公告)日：2008-07-31
申请号：US12098303
申请日：2008-04-04
申请人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
发明人： William A. Hughes , Vydhyanathan Kalyanasundharam , Kiran K. Bondalapati , Philip E. Madrid , Stephen C. Ennis
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F15/8007
摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
摘要翻译：在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。在另一个实施例中，节点包括处理器核心和节点控制器。节点控制器包括由处理器核共享的队列。处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

8. 发明申请

US20120144122A1 METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION 有权
标题翻译：用于加速共享数据迁移的方法和装置
公开(公告)号：US20120144122A1
公开(公告)日：2012-06-07
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/02 , G06F12/00 , G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores is disclosed.
摘要翻译：公开了一种用于在核之间加速共享数据迁移的方法和装置。

9. 发明授权

US08732410B2 Method and apparatus for accelerated shared data migration 有权
标题翻译：加速共享数据迁移的方法和装置
公开(公告)号：US08732410B2
公开(公告)日：2014-05-20
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.
摘要翻译：一种用于加速内核之间共享数据迁移的方法和装置。使用始终迁移协议，当迁移探测器以修改或归属状态命中目录条目时，该条目将转换为所有状态，并且发送源完成命令，而不向缓存目录发送缓存块所有权或状态信息。

10. 发明申请

US20120159080A1 NEIGHBOR CACHE DIRECTORY 审中-公开
标题翻译：邻居缓存目录
公开(公告)号：US20120159080A1
公开(公告)日：2012-06-21
申请号：US12969343
申请日：2010-12-15
申请人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
发明人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0895 , G06F2212/603
摘要： A method and apparatus for utilizing a higher-level cache as a neighbor cache directory in a multi-processor system are provided. In the method and apparatus, when the data field of a portion or all of the cache is unused, a remaining portion of the cache is repurposed for usage as neighbor cache directory. The neighbor cache provides a pointer to another cache in the multi-processor system storing memory data. The neighbor cache directory can be searched in the same manner as a data cache.
摘要翻译：提供了一种用于在多处理器系统中利用高级缓存作为相邻高速缓存目录的方法和装置。在所述方法和装置中，当高速缓存的一部分或全部的数据字段未使用时，高速缓存的剩余部分被重新利用以用作相邻高速缓存目录。邻居缓存提供指向存储存储器数据的多处理器系统中的另一高速缓存的指针。可以以与数据高速缓存相同的方式搜索邻居缓存目录。

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