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1. 发明授权

US08195887B2 Processor power management and method 有权
标题翻译：处理器电源管理和方法
公开(公告)号：US08195887B2
公开(公告)日：2012-06-05
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

2. 发明申请

US20100185820A1 PROCESSOR POWER MANAGEMENT AND METHOD 有权
标题翻译：处理器功率管理和方法
公开(公告)号：US20100185820A1
公开(公告)日：2010-07-22
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译：公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

3. 发明申请

US20120144122A1 METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION 有权
标题翻译：用于加速共享数据迁移的方法和装置
公开(公告)号：US20120144122A1
公开(公告)日：2012-06-07
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/02 , G06F12/00 , G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores is disclosed.
摘要翻译：公开了一种用于在核之间加速共享数据迁移的方法和装置。

4. 发明授权

US08732410B2 Method and apparatus for accelerated shared data migration 有权
标题翻译：加速共享数据迁移的方法和装置
公开(公告)号：US08732410B2
公开(公告)日：2014-05-20
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.
摘要翻译：一种用于加速内核之间共享数据迁移的方法和装置。使用始终迁移协议，当迁移探测器以修改或归属状态命中目录条目时，该条目将转换为所有状态，并且发送源完成命令，而不向缓存目录发送缓存块所有权或状态信息。

5. 发明申请

US20120159080A1 NEIGHBOR CACHE DIRECTORY 审中-公开
标题翻译：邻居缓存目录
公开(公告)号：US20120159080A1
公开(公告)日：2012-06-21
申请号：US12969343
申请日：2010-12-15
申请人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
发明人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0895 , G06F2212/603
摘要： A method and apparatus for utilizing a higher-level cache as a neighbor cache directory in a multi-processor system are provided. In the method and apparatus, when the data field of a portion or all of the cache is unused, a remaining portion of the cache is repurposed for usage as neighbor cache directory. The neighbor cache provides a pointer to another cache in the multi-processor system storing memory data. The neighbor cache directory can be searched in the same manner as a data cache.
摘要翻译：提供了一种用于在多处理器系统中利用高级缓存作为相邻高速缓存目录的方法和装置。在所述方法和装置中，当高速缓存的一部分或全部的数据字段未使用时，高速缓存的剩余部分被重新利用以用作相邻高速缓存目录。邻居缓存提供指向存储存储器数据的多处理器系统中的另一高速缓存的指针。可以以与数据高速缓存相同的方式搜索邻居缓存目录。

6. 发明申请

US20120155273A1 SPLIT TRAFFIC ROUTING IN A PROCESSOR 审中-公开
标题翻译：分处交通运输路线
公开(公告)号：US20120155273A1
公开(公告)日：2012-06-21
申请号：US12968857
申请日：2010-12-15
申请人： William A. Hughes , Chenping Yang , Michael K. Fertig , Kevin M. Lepak
发明人： William A. Hughes , Chenping Yang , Michael K. Fertig , Kevin M. Lepak
IPC分类号： H04L12/26
CPC分类号： G06F15/17312
摘要： A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.
摘要翻译：多芯片模块配置包括两个处理器，每个处理器具有两个节点，每个节点包括多个核心或计算单元。每个节点通过高带宽或低带宽的链路连接到其他节点。根据路由表和/或优化带宽使用和业务拥塞控制的控制寄存器，在每个节点处控制节点之间的业务路由。

7. 发明申请

US20130077701A1 METHOD AND INTEGRATED CIRCUIT FOR ADJUSTING THE WIDTH OF AN INPUT/OUTPUT LINK 审中-公开
标题翻译：用于调整输入/输出链路宽度的方法和集成电路
公开(公告)号：US20130077701A1
公开(公告)日：2013-03-28
申请号：US13243086
申请日：2011-09-23
申请人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
发明人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
IPC分类号： H04L27/00
CPC分类号： G06F1/3253 , G06F13/4273 , H04L25/14 , H04W28/18 , Y02D10/151
摘要： A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.
摘要翻译：描述了一种用于调整在发射机和接收机之间建立的输入/输出（I / O）链路的比特宽度的方法和装置。 I / O链路具有多个位通道。响应于检测到已经达到I / O链路的比特宽度调整阈值，发射机可以向接收机发送识别I / O链路的至少一个所选比特通道的命令，该I / O链路将被断电或上电。

8. 发明授权

US07640399B1 Mostly exclusive shared cache management policies 有权
标题翻译：大多数独家共享缓存管理策略
公开(公告)号：US07640399B1
公开(公告)日：2009-12-29
申请号：US11432707
申请日：2006-05-10
申请人： Kevin M. Lepak , Roger D. Isaac
发明人： Kevin M. Lepak , Roger D. Isaac
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/0811
摘要： A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candidates for replacement. Data entries which have been identified as candidates for replacement may be removed as candidates for replacement in response to detecting the data entry corresponds to data which is shared by at least two of the plurality of processing entities. The circuitry may maintain an indication as to which of the processing entities caused an initial allocation of data into the shared cache. When the circuitry detects that a particular data item is accessed by a processing entity other than a processing entity which caused an allocation of the given data item, the data item may be deemed classified as shared data.
摘要翻译：一种用于管理存储器系统的系统和方法。系统包括多个处理实体和由处理实体共享的高速缓存。响应于替换事件，电路可以识别作为替换候选的共享缓存的数据条目。已经被识别为替换候选的数据条目可以作为响应于检测到数据条目的替换候选而被去除，对应于由多个处理实体中的至少两个共享的数据。电路可以保持关于哪个处理实体将数据初始分配到共享高速缓存中的指示。当电路检测到特定数据项被除了导致给定数据项的分配的处理实体之外的处理实体访问时，数据项可被认为被分类为共享数据。

9. 发明申请

US20120144124A1 METHOD AND APPARATUS FOR MEMORY ACCESS UNITS INTERACTION AND OPTIMIZED MEMORY SCHEDULING 审中-公开
标题翻译：用于存储器访问单元交互和优化记忆调度的方法和装置
公开(公告)号：US20120144124A1
公开(公告)日：2012-06-07
申请号：US12962042
申请日：2010-12-07
申请人： Kevin M. Lepak , Benjamin Tsien , Todd Rafacz
发明人： Kevin M. Lepak , Benjamin Tsien , Todd Rafacz
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A method and an apparatus for modulating the prefetch training of a memory-side prefetch unit (MS-PFU) are described. An MS-PFU trains on memory access requests it receives from processors and their processor-side prefetch units (PS-PFUs). In the method and apparatus, an MS-PFU modulates its training based on one or more of a PS-PFU memory access request, a PS-PFU memory access request type, memory utilization, or the accuracy of MS-PFU prefetch requests.
摘要翻译：描述了用于调制存储器侧预取单元（MS-PFU）的预取训练的方法和装置。 MS-PFU对从处理器及其处理器端预取单元（PS-PFU）接收的存储器访问请求进行训练。在该方法和装置中，MS-PFU基于PS-PFU存储器访问请求，PS-PFU存储器访问请求类型，存储器利用率或MS-PFU预取请求的准确性中的一个或多个来调制其训练。

10. 发明授权

US07603522B1 Blocking aggressive neighbors in a cache subsystem 有权
标题翻译：阻止缓存子系统中的攻击性邻居
公开(公告)号：US07603522B1
公开(公告)日：2009-10-13
申请号：US11432706
申请日：2006-05-10
申请人： Kevin M. Lepak , Roger D. Isaac
发明人： Kevin M. Lepak , Roger D. Isaac
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/084 , G06F12/128
摘要： A system and method for managing a cache subsystem. A system comprises a plurality of processing entities, a cache shared by the plurality of processing entities, and circuitry configured to manage allocations of data into the cache. Cache controller circuitry is configured to allocate data in the cache at a less favorable position in the replacement stack in response to determining a processing entity which corresponds to the allocated data has relatively poor cache behavior compared to other processing entities. The circuitry is configured to track a relative hit rate for each processing entity, such as a thread or processor core. A figure of merit may be determined for each processing entity which reflects how well a corresponding processing entity is behaving with respect to the cache. Processing entities which have a relatively low figure of merit may have their data allocated in the shared cache at a lower level in the cache replacement stack.
摘要翻译：一种用于管理缓存子系统的系统和方法。系统包括多个处理实体，由多个处理实体共享的高速缓存器，以及被配置为管理数据到高速缓存中的分配的电路。高速缓存控制器电路被配置为响应于确定与所分配的数据相对应的处理实体与其他处理实体相比具有相对较差的缓存行为，在替换栈中的不太有利的位置处在高速缓存中分配数据。电路被配置为跟踪每个处理实体（例如线程或处理器核心）的相对命中率。可以为反映相应处理实体相对于高速缓存行为的程度的每个处理实体确定品质因数。具有相对较低品质因数的处理实体可以将数据分配在高速缓存替换堆栈中的较低级别的共享高速缓存中。

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