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1. 发明授权

US07836259B1 Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy 有权
标题翻译：预取单元，用于缓存存储器层次结构的高速缓存存储器子系统
公开(公告)号：US07836259B1
公开(公告)日：2010-11-16
申请号：US10817693
申请日：2004-04-02
申请人： Michael A. Filippo , James K. Pickett , Roger D. Isaac
发明人： Michael A. Filippo , James K. Pickett , Roger D. Isaac
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.
摘要翻译：用于缓存子系统的预取单元。预取单元包括耦合到预取单元的流存储器。流存储器可以包括被配置为存储多个条目的多个位置，每个条目对应于预取地址的相应范围。预取控制可以被配置为响应于接收包括在多个条目中的任何一个的预取地址的相应范围内的地址的高速缓存访问请求来预取地址。

2. 发明授权

US06976147B1 Stride-based prefetch mechanism using a prediction confidence value 有权
标题翻译：基于步长的预取机制使用预测置信度值
公开(公告)号：US06976147B1
公开(公告)日：2005-12-13
申请号：US10347828
申请日：2003-01-21
申请人： Roger D. Isaac , Mitchell Alsup
发明人： Roger D. Isaac , Mitchell Alsup
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A prefetch mechanism includes a prefetch predictor table coupled to a prefetch control. The prefetch predictor table may include a plurality of locations configured to store a plurality of entries each indicative of a stride between a respective pair of memory requests. Each of the plurality of entries may be stored in a respective one of the plurality of locations dependent upon a value of an earlier stride. The prefetch control may be configured to prefetch an address based upon a given one of the plurality of entries in the prefetch predictor table.
摘要翻译：预取机制包括耦合到预取控制的预取预测器表。预取预测器表可以包括被配置为存储多个条目的多个位置，每个条目指示相应的一对存储器请求之间的跨步。多个条目中的每一个可以存储在多个位置中的相应一个位置，这取决于较早步幅的值。预取控制可以被配置为基于预取预测器表中的多个条目中的给定一个预取地址。

3. 发明申请

US20190139367A1 MECHANISM FOR SPONSORSHIP WITH CONTEXTUAL TRANSACTIONS 审中-公开
公开(公告)号：US20190139367A1
公开(公告)日：2019-05-09
申请号：US16030842
申请日：2018-07-09
申请人： Roger D. Isaac
发明人： Roger D. Isaac
IPC分类号： G07F17/32 , G06Q50/34
摘要： At a high-level, method to enable viewers of online or televised gaming tournaments to actively participate in the tournament through monetary or other means.

4. 发明申请

US20140024314A1 SMART CONNECTORS AND ASSOCIATED COMMUNICATIONS LINKS 有权
标题翻译：智能连接器和相关通信链接
公开(公告)号：US20140024314A1
公开(公告)日：2014-01-23
申请号：US13969565
申请日：2013-08-17
申请人： Gary D. McCormack , Ian A. Kyles , Roger D. Isaac
发明人： Gary D. McCormack , Ian A. Kyles , Roger D. Isaac
IPC分类号： H04W76/04
CPC分类号： H04W76/043 , H04B1/40 , H04B5/0031 , H04W52/0229 , H04W76/23 , H05K1/0243 , H05K1/0259 , H05K2201/10098 , Y02D70/142 , Y02D70/144 , Y02D70/166 , Y02D70/40 , Y02D70/42
摘要： “Smart” connectors with embedded processors, measurement circuits and control circuits are disclosed for establishing a “contactless” radio frequency (RF) electromagnetic (EM) Extremely High Frequency (EHF) communications link between two electronic devices having host systems. The connectors are capable of monitoring, controlling, and directing (managing) link operation to dynamically adapt to conditions, as well as monitoring and altering (or modifying) data passing through the connector, and selecting a protocol suitable for a communications session. The connectors are capable of identifying the type of content being transferred, providing authentication and security services, and enabling application support for the host systems based on the type of connection or the type of content. The connectors may operate independently of the host systems, and may perform at least one of sensing proximity of a nearby object; detecting a shape of a nearby object; and detecting vibrations.
摘要翻译：公开了具有嵌入式处理器，测量电路和控制电路的“智能”连接器，用于在具有主机系统的两个电子设备之间建立“非接触”射频（RF）电磁（EM）极高频（EHF）通信链路。连接器能够监视，控制和指导（管理）链接操作以动态地适应条件，以及监视和改变（或修改）通过连接器的数据，并选择适合通信会话的协议。连接器能够识别正在传送的内容的类型，提供认证和安全服务，并且基于连接的类型或内容的类型来为主机系统启用应用支持。连接器可以独立于主机系统操作，并且可以执行感测邻近对象的接近中的至少一个; 检测附近物体的形状; 并检测振动。

5. 发明申请

US20130217336A1 CONTACTLESS DATA TRANSFER SYSTEMS AND METHODS 有权
标题翻译：无连续数据传输系统和方法
公开(公告)号：US20130217336A1
公开(公告)日：2013-08-22
申请号：US13848735
申请日：2013-03-22
申请人： Gary D. McCormack , Roger D. Isaac
发明人： Gary D. McCormack , Roger D. Isaac
IPC分类号： H04B7/00
CPC分类号： H04B7/00 , H04W8/085
摘要： Data may be transferred from a communication subsystem of a first device to a communication subsystem of a second device contactlessly, at high speed, and without intervention by host processors of either device. Devices may be programmed or personalized at the factory or warehouse, and may personalized at a warehouse or at a point of sale while in the box. Various modes of operation and use scenarios are described. Portions of the devices themselves, or a transmission path between the devices may be shielded against snooping by a material which degrades an EHF signal passing therethrough.
摘要翻译：数据可以从第一设备的通信子系统到第二设备的通信子系统以高速无接触地传送，并且不经任何一个设备的主机处理器干预。设备可以在工厂或仓库进行编程或个性化，并且可以在箱子中的仓库或销售点进行个性化处理。描述了各种操作和使用方案。器件本身的一部分或器件之间的传输路径可以通过降低通过其中的EHF信号的材料来屏蔽以进行窥探。

6. 发明授权

US07133975B1 Cache memory system including a cache memory employing a tag including associated touch bits 有权
标题翻译：高速缓冲存储器系统包括采用包括相关触摸位的标签的高速缓冲存储器
公开(公告)号：US07133975B1
公开(公告)日：2006-11-07
申请号：US10347827
申请日：2003-01-21
申请人： Roger D. Isaac , Mitchell Alsup
发明人： Roger D. Isaac , Mitchell Alsup
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811
摘要： A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a first plurality of cache lines of data. The second cache storage may store a second plurality of cache lines of data. Further the second cache memory subsystem includes a tag storage which may store a plurality of tags each corresponding to a respective cache line of the second plurality of cache lines. In addition, each of said plurality of tags includes an associated bit indicative of whether a copy of the corresponding respective cache line is stored within the first cache memory subsystem.
摘要翻译：一种高速缓冲存储器系统，包括采用包括相关触摸位的标签的高速缓冲存储器。该系统包括具有第一高速缓冲存储器的第一缓存存储器子系统和包括第二高速缓存存储器的第二高速缓存存储器子系统。第一高速缓存存储器可以存储数据的第一多个高速缓存行。第二高速缓存存储器可以存储第二多个高速缓存数据行。此外，第二高速缓存存储器子系统包括可以存储多个标签的标签存储器，每个标签对应于第二多个高速缓存行的相应高速缓存行。另外，所述多个标签中的每一个包括指示相应的相应高速缓存行的副本是否存储在第一高速缓冲存储器子系统内的关联位。

7. 发明授权

US08510487B2 Hybrid interface for serial and parallel communication 有权
标题翻译：用于串行和并行通信的混合接口
公开(公告)号：US08510487B2
公开(公告)日：2013-08-13
申请号：US12704417
申请日：2010-02-11
申请人： Alan T. Ruberg , Roger D. Isaac
发明人： Alan T. Ruberg , Roger D. Isaac
IPC分类号： G06F13/12 , G06F13/36
CPC分类号： G06F13/4204 , G06F13/4045 , G06F13/4282 , H04L29/10 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.
摘要翻译：本发明的实施例一般涉及用于串行和并行通信的混合接口。一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚，以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及通过第二多个引脚在第二模式中发送或接收串行数据。

8. 发明申请

US20110196997A1 HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION 有权
标题翻译：用于串行和并行通信的混合接口
公开(公告)号：US20110196997A1
公开(公告)日：2011-08-11
申请号：US12704417
申请日：2010-02-11
申请人： Alan T. Ruberg , Roger D. Isaac
发明人： Alan T. Ruberg , Roger D. Isaac
IPC分类号： G06F13/42 , H03L7/08
CPC分类号： G06F13/4204 , G06F13/4045 , G06F13/4282 , H04L29/10 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.
摘要翻译：本发明的实施例一般涉及用于串行和并行通信的混合接口。一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚，以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及通过第二多个引脚在第二模式中发送或接收串行数据。

9. 发明授权

US07603522B1 Blocking aggressive neighbors in a cache subsystem 有权
标题翻译：阻止缓存子系统中的攻击性邻居
公开(公告)号：US07603522B1
公开(公告)日：2009-10-13
申请号：US11432706
申请日：2006-05-10
申请人： Kevin M. Lepak , Roger D. Isaac
发明人： Kevin M. Lepak , Roger D. Isaac
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/084 , G06F12/128
摘要： A system and method for managing a cache subsystem. A system comprises a plurality of processing entities, a cache shared by the plurality of processing entities, and circuitry configured to manage allocations of data into the cache. Cache controller circuitry is configured to allocate data in the cache at a less favorable position in the replacement stack in response to determining a processing entity which corresponds to the allocated data has relatively poor cache behavior compared to other processing entities. The circuitry is configured to track a relative hit rate for each processing entity, such as a thread or processor core. A figure of merit may be determined for each processing entity which reflects how well a corresponding processing entity is behaving with respect to the cache. Processing entities which have a relatively low figure of merit may have their data allocated in the shared cache at a lower level in the cache replacement stack.
摘要翻译：一种用于管理缓存子系统的系统和方法。系统包括多个处理实体，由多个处理实体共享的高速缓存器，以及被配置为管理数据到高速缓存中的分配的电路。高速缓存控制器电路被配置为响应于确定与所分配的数据相对应的处理实体与其他处理实体相比具有相对较差的缓存行为，在替换栈中的不太有利的位置处在高速缓存中分配数据。电路被配置为跟踪每个处理实体（例如线程或处理器核心）的相对命中率。可以为反映相应处理实体相对于高速缓存行为的程度的每个处理实体确定品质因数。具有相对较低品质因数的处理实体可以将数据分配在高速缓存替换堆栈中的较低级别的共享高速缓存中。

10. 发明申请

US20140273852A1 VIRTUALIZED PHYSICAL LAYER ADAPTED FOR EHF CONTACTLESS COMMUNICATION 有权
标题翻译：虚拟化物理层适用于EHF联络通信
公开(公告)号：US20140273852A1
公开(公告)日：2014-09-18
申请号：US14205658
申请日：2014-03-12
申请人： Gary D. McCormack , Ian A. Kyles , Roger D. Isaac
发明人： Gary D. McCormack , Ian A. Kyles , Roger D. Isaac
IPC分类号： H04W76/02
CPC分类号： H04B5/0031 , H04B5/0037 , H04W76/10 , H04W76/14
摘要： A Physical Layer (PHY) of a host system of an electronic device may be implemented as a contactless PHY (cPHY) for extremely high frequency (EHF) contactless communication and the operation of EHF transmitters (TX), receivers (RX) and transceivers (EHF-XCVR) in an extremely high frequency integrated circuit (EHF IC) of the electronic device. The Host-cPHY translates logical communications requests from the Link Layer (LINK) into hardware-specific operations to affect transmission or reception of signals over an EHF contactless link. The Link Layer (LINK) may also be optimized as a contactless Link Layer (cLINK) for EHF contactless communication. A virtualized contactless Physical Layer (VcPHY) may comprise a contactless Physical Layer (Host-cPHY), and a contactless Link Layer (cLINK) for coupling a conventional Link Layer (LINK) with the contactless Physical Layer (Host-cPHY). Multiple data streams may be transported over the EHF contactless link over a range of frequencies.
摘要翻译：电子设备的主机系统的物理层（PHY）可以实现为用于极高频（EHF）非接触通信的无触点PHY（cPHY）和EHF发射机（TX），接收机（RX）和收发器 EHF-XCVR）在电子设备的极高频集成电路（EHF IC）中。 Host-cPHY将来自链路层（LINK）的逻辑通信请求转换为特定于硬件的操作，以影响通过EHF非接触式链路传输或接收信号。链路层（LINK）也可以被优化为用于EHF非接触通信的非接触式链路层（cLINK）。虚拟化非接触物理层（VcPHY）可以包括用于将常规链路层（LINK）与非接触物理层（Host-cPHY）耦合的非接触式物理层（Host-cPHY）和非接触式链路层（cLINK）。多个数据流可以在一个频率范围上通过EHF非接触式链路传输。

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