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1. 发明申请

US20080285196A1 OVER-VOLTAGE INDICATOR AND RELATED CIRCUIT AND METHOD 失效
标题翻译：过电压指示器及相关电路及方法
公开(公告)号：US20080285196A1
公开(公告)日：2008-11-20
申请号：US11934767
申请日：2007-11-03
申请人： Wen-Ching Hsiung , Jeng-Dau Chang , Chia-Liang Lai , Kuan-Yu Chen
发明人： Wen-Ching Hsiung , Jeng-Dau Chang , Chia-Liang Lai , Kuan-Yu Chen
IPC分类号： H02H9/04 , H02H3/20
CPC分类号： H03K17/223 , H03K17/08 , H03K17/18 , H03K19/00315 , H03K2217/0018 , H03K2217/96054
摘要： Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.
摘要翻译：过电压指示器及相关电路及方法。过电压指示器可以与芯片的I / O电路一起工作，用于检测I / O焊盘中的过电压并相应地提供指示信号。当不发生过电压时，过电压指示器继续检测I / O焊盘的信号电平，并保持指示信号为低电平。一旦检测到过电压，则过电压指示器暂停检测，在指示信号中置高电平，并且周期性地恢复检测直到检测到过电压结束。通过指示信号提供的通知，芯片的核心单元可以执行正常的操作，以减少由过电压引起的潜在损害。

2. 发明申请

US20090219056A1 SIGNAL DETECTION CIRCUIT WITH DEGLITCH AND METHOD THEREOF 有权
标题翻译：信号检测电路及其方法
公开(公告)号：US20090219056A1
公开(公告)日：2009-09-03
申请号：US12040094
申请日：2008-02-29
申请人： Wen-Ching Hsiung , Kuan-Yu Chen , Jeng-Dau Chang , Chia-Liang Lai
发明人： Wen-Ching Hsiung , Kuan-Yu Chen , Jeng-Dau Chang , Chia-Liang Lai
IPC分类号： G01R29/02 , H03K9/08
CPC分类号： H03K5/1252 , H03K5/082
摘要： A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.
摘要翻译：信号检测电路用于检测差分输入信号的信号静噪以产生相应的数字输出信号。信号检测电路包括：参考电压发生器，用于产生共模电压跟踪输入信号的共模电压的参考电压; 实时信号判断电路，对输入信号和参考电压之间的差异进行实时整流和放大; 和去离差电路，对实时信号判断电路的输出信号进行采样和/或放大，并将采样结果变换为数字输出信号，以反映差分输入信号的信号静噪。

3. 发明授权

US07706115B2 Over-voltage indicator and related circuit and method 失效
标题翻译：过电压指示器及相关电路及方法
公开(公告)号：US07706115B2
公开(公告)日：2010-04-27
申请号：US11934767
申请日：2007-11-03
申请人： Wen-Ching Hsiung , Jeng-Dau Chang , Chia-Liang Lai , Kuan-Yu Chen
发明人： Wen-Ching Hsiung , Jeng-Dau Chang , Chia-Liang Lai , Kuan-Yu Chen
IPC分类号： H02H3/027
CPC分类号： H03K17/223 , H03K17/08 , H03K17/18 , H03K19/00315 , H03K2217/0018 , H03K2217/96054
摘要： Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.
摘要翻译：过电压指示器及相关电路及方法。过电压指示器可以与芯片的I / O电路一起工作，用于检测I / O焊盘中的过电压并相应地提供指示信号。当不发生过电压时，过电压指示器继续检测I / O焊盘的信号电平，并保持指示信号为低电平。一旦检测到过电压，则过电压指示器暂停检测，在指示信号中置高电平，并且周期性地恢复检测直到检测到过电压结束。通过指示信号提供的通知，芯片的核心单元可以执行正常的操作，以减少由过电压引起的潜在损害。

4. 发明申请

US20090134913A1 SIGNAL COMPARISON CIRCUIT 有权
标题翻译：信号比较电路
公开(公告)号：US20090134913A1
公开(公告)日：2009-05-28
申请号：US11945053
申请日：2007-11-26
申请人： Wen-Ching Hsiung , Chia-Liang Lai , Kuan-Yu Chen , Jeng-Dau Chang
发明人： Wen-Ching Hsiung , Chia-Liang Lai , Kuan-Yu Chen , Jeng-Dau Chang
IPC分类号： G01R19/165
CPC分类号： G01R19/16557 , H03F3/45183 , H03F3/45475 , H03F2200/261 , H03F2200/435 , H03F2203/45138 , H03F2203/45391 , H03F2203/45458 , H03F2203/45466 , H03K5/082 , H03K5/2481
摘要： A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.
摘要翻译：提供信号比较电路。信号比较电路包括第一放大器，第二放大器，峰值检测器和比较器。第一个放大器是零峰值放大器。第一放大器接收并放大数据信号。第二放大器接收并放大参考电压。峰值检测器耦合到第一和第二放大器，用于检测和维持放大的数据信号和放大的参考电压的最大值，然后输出维持的数据信号和保持的参考电压。比较器耦合到峰值检测器，用于将保持的数据信号与维持的参考电压进行比较，并输出比较结果。

5. 发明授权

US07825697B2 Signal detection circuit with deglitch and method thereof 有权
标题翻译：信号检测电路及其方法
公开(公告)号：US07825697B2
公开(公告)日：2010-11-02
申请号：US12040094
申请日：2008-02-29
申请人： Wen-Ching Hsiung , Kuan-Yu Chen , Jeng-Dau Chang , Chia-Liang Lai
发明人： Wen-Ching Hsiung , Kuan-Yu Chen , Jeng-Dau Chang , Chia-Liang Lai
IPC分类号： H03K9/08
CPC分类号： H03K5/1252 , H03K5/082
摘要： A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.
摘要翻译：信号检测电路用于检测差分输入信号的信号静噪以产生相应的数字输出信号。信号检测电路包括：参考电压发生器，用于产生共模电压跟踪输入信号的共模电压的参考电压; 实时信号判断电路，对输入信号和参考电压之间的差异进行实时整流和放大; 和去离差电路，对实时信号判断电路的输出信号进行采样和/或放大，将采样结果变换为数字输出信号，以反映差分输入信号的信号静噪。

6. 发明授权

US07782095B2 Signal comparison circuit 有权
标题翻译：信号比较电路
公开(公告)号：US07782095B2
公开(公告)日：2010-08-24
申请号：US11945053
申请日：2007-11-26
申请人： Wen-Ching Hsiung , Chia-Liang Lai , Kuan-Yu Chen , Jeng-Dau Chang
发明人： Wen-Ching Hsiung , Chia-Liang Lai , Kuan-Yu Chen , Jeng-Dau Chang
IPC分类号： H03K5/153
CPC分类号： G01R19/16557 , H03F3/45183 , H03F3/45475 , H03F2200/261 , H03F2200/435 , H03F2203/45138 , H03F2203/45391 , H03F2203/45458 , H03F2203/45466 , H03K5/082 , H03K5/2481
摘要： A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.
摘要翻译：提供信号比较电路。信号比较电路包括第一放大器，第二放大器，峰值检测器和比较器。第一个放大器是零峰值放大器。第一放大器接收并放大数据信号。第二放大器接收并放大参考电压。峰值检测器耦合到第一和第二放大器，用于检测和维持放大的数据信号和放大的参考电压的最大值，然后输出维持的数据信号和保持的参考电压。比较器耦合到峰值检测器，用于将保持的数据信号与维持的参考电压进行比较，并输出比较结果。

7. 发明授权

US07764088B2 Frequency detection circuit and detection method for clock data recovery circuit 有权
标题翻译：时钟数据恢复电路的频率检测电路和检测方法
公开(公告)号：US07764088B2
公开(公告)日：2010-07-27
申请号：US12237025
申请日：2008-09-24
申请人： Kuan-Yu Chen , Wen-Ching Hsiung , Cheng-Tao Chang , Chia-Liang Lai
发明人： Kuan-Yu Chen , Wen-Ching Hsiung , Cheng-Tao Chang , Chia-Liang Lai
IPC分类号： H03D13/00
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/085 , H03L7/089
摘要： A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.
摘要翻译：提供适用于时钟数据恢复（CDR）电路的频率检测电路及其检测方法。频率检测电路包括相位检测器，第一延迟器，频率检测器和逻辑电路。相位检测器根据由CDR电路提供的第一时钟信号对数据信号进行采样，并根据采样提供相位指令信号。第一延迟器延迟第一时钟信号以获得第二时钟信号。频率检测器根据第二时钟信号对数据信号进行采样，并根据采样提供频率指令信号。逻辑电路根据相位指令信号和频率指令信号生成时钟指令信号。 CDR电路根据时钟指令信号的状态来调整第一时钟信号的频率。

8. 发明申请

US20100073045A1 FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT 有权
标题翻译：频率检测电路和时钟数据恢复电路的检测方法
公开(公告)号：US20100073045A1
公开(公告)日：2010-03-25
申请号：US12237025
申请日：2008-09-24
申请人： Kuan-Yu Chen , Wen-Ching Hsiung , Cheng-Tao Chang , Chia-Liang Lai
发明人： Kuan-Yu Chen , Wen-Ching Hsiung , Cheng-Tao Chang , Chia-Liang Lai
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/085 , H03L7/089
摘要： A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.
摘要翻译：提供适用于时钟数据恢复（CDR）电路的频率检测电路及其检测方法。频率检测电路包括相位检测器，第一延迟器，频率检测器和逻辑电路。相位检测器根据由CDR电路提供的第一时钟信号对数据信号进行采样，并根据采样提供相位指令信号。第一延迟器延迟第一时钟信号以获得第二时钟信号。频率检测器根据第二时钟信号对数据信号进行采样，并根据采样提供频率指令信号。逻辑电路根据相位指令信号和频率指令信号生成时钟指令信号。 CDR电路根据时钟指令信号的状态来调整第一时钟信号的频率。

9. 发明申请

US20160087636A1 CLOCK GENERATING APPARATUS AND FRACTIONAL FREQUENCY DIVIDER THEREOF 有权
标题翻译：时钟发生装置及其分频器
公开(公告)号：US20160087636A1
公开(公告)日：2016-03-24
申请号：US14527779
申请日：2014-10-30
申请人： Chia-Liang Lai , Song-Rong Han , Jung-Yu Chang , Wei-Ming Lin
发明人： Chia-Liang Lai , Song-Rong Han , Jung-Yu Chang , Wei-Ming Lin
IPC分类号： H03K21/02
CPC分类号： H03L7/1976 , H03K21/023 , H03K23/68 , H03L7/1974
摘要： A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.
摘要翻译：提供时钟发生装置及其分数分频器。分数分频器包括分频器（FD），多个采样器，选择器和控制电路。 FD的输入端耦合到多相频率发生电路的输出端。采样器的输入端耦合到FD的输出端。采样器的触发端接收采样时钟信号。选择器的输入端耦合到采样器的输出端。选择器的输出端耦合到多相频率发生电路的反馈端。控制电路向选择器的控制端提供分数代码，以便控制选择器选择性地将一个采样器的输出端耦合到多相频率发生电路的反馈端。

10. 发明申请

US20110006817A1 TRIANGULAR WAVE GENERATOR, SSCG UTILIZING THE TRIANGULAR WAVE GENERATOR, AND RELATED METHOD THEREOF 审中-公开
标题翻译：三角波发生器，采用三角波发生器的SSCG及其相关方法
公开(公告)号：US20110006817A1
公开(公告)日：2011-01-13
申请号：US12499781
申请日：2009-07-08
申请人： Song-Rong Han , Kuo-Hsiung Wu , Chia-Liang Lai
发明人： Song-Rong Han , Kuo-Hsiung Wu , Chia-Liang Lai
IPC分类号： H03K4/06
CPC分类号： H03K4/06 , G06F1/08 , H03K3/84
摘要： A triangular wave generator, comprising: a first frequency divider, for utilizing a first positive integer to divide a first frequency of a first periodical signal to generate a first frequency-divided signal; a second frequency divider, for utilizing a second positive integer to divide a second frequency, which equals the first frequency multiplying a third positive integer, of a second periodical signal to generate a second frequency-divided signal; and an up/down counter, for generating a triangular wave first and second frequency-divided frequencies respectively belonging to first and second frequency divided signals; wherein a frequency of the triangular wave equals to the first frequency-divided frequency, and an amplitude of the triangular wave is determined according to a ratio of the first and second frequency-divided frequencies.
摘要翻译：一种三角波发生器，包括：第一分频器，用于利用第一正整数来分频第一周期信号的第一频率以产生第一分频信号; 第二分频器，用于利用第二正整数来分频第二周期信号的等于第三正整数的第一频率的第二频率以产生第二分频信号; 以及用于产生分别属于第一和第二分频信号的三角波第一和第二分频频率的向上/向下计数器; 其中所述三角波的频率等于所述第一分频频率，并且根据所述第一和第二分频频率的比率来确定所述三角波的振幅。

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