专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09891250B2 Bidirectional voltage differentiator circuit 有权
公开(公告)号：US09891250B2
公开(公告)日：2018-02-13
申请号：US15641088
申请日：2017-07-03
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Yijun Duan
IPC分类号： G01R19/12 , H03L7/00 , H05B33/08 , G01R19/165
CPC分类号： G01R19/12 , G01R19/16557 , H05B33/0845 , H05B33/0887
摘要： A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.

2. 发明授权

US07605616B2 Voltage detector circuit 有权
标题翻译：电压检测电路
公开(公告)号：US07605616B2
公开(公告)日：2009-10-20
申请号：US11975097
申请日：2007-10-16
申请人： Koji Shimbayashi
发明人： Koji Shimbayashi
IPC分类号： H03K5/153
CPC分类号： G01R19/16557 , G01R19/16571 , G11C5/143 , G11C5/147
摘要： A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference current generating section includes a voltage-controlled current source that includes a control terminal, a reference terminal and an output terminal. The reference current generating section generates an output current that serves as a reference current and output to a current mirroring circuit. The detecting section includes a number of voltage-controlled current sources each with the same configuration as the voltage-controlled current sources in the current generating section. A potential to be detected is input into the detecting section. A target potential is calculated as the set potential multiplied by the number of voltage-controlled current sources in the detecting section. When the absolute value of the potential to be detected equals the target potential, the currents in each of the voltage-controlled current sources in the detecting section is set equal to the set potential. Due to the equivalent configurations of the voltage-controlled current sources, the current flowing in the reference current generating section is balanced with, and becomes equal to the current in the detecting section. The detection is made by current comparison between the reference current output from the reference current generating section and the detection current flowing in the detecting section.
摘要翻译：一种电压检测电路，用于精确地检测由于晶体管特性和阈值电压的变化而不受波动影响的电压。电压检测电路包括基准电流产生部分和检测部分。基准电流产生部分包括一个包括控制端子，参考端子和输出端子的压控电流源。参考电流产生部分产生用作参考电流并输出到电流镜像电路的输出电流。检测部分包括多个电压控制电流源，每个具有与电流产生部分中的电压控制电流源相同的配置。将被检测的电位输入到检测部。计算目标电位作为设定电位乘以检测部中的电压控制电流源的数量。当待检测电位的绝对值等于目标电位时，检测部分中每个电压控制电流源中的电流设定为等于设定电位。由于电压控制电流源的等效结构，在参考电流产生部分中流动的电流与检测部分中的电流平衡并变成等于电流。通过从参考电流产生部分输出的参考电流与在检测部分中流动的检测电流之间的电流比较来进行检测。

3. 发明授权

US07183792B2 Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same 有权
标题翻译：用于检测集成电路的工作模式的方法和系统，以及包括其的存储器件
公开(公告)号：US07183792B2
公开(公告)日：2007-02-27
申请号：US10405328
申请日：2003-04-01
申请人： Kenneth W. Marr
发明人： Kenneth W. Marr
IPC分类号： H03K19/00 , H03K19/173 , G06F11/00
CPC分类号： G11C29/50004 , G01R19/16557 , G01R31/31701 , G11C11/41 , G11C29/46
摘要： A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically.
摘要翻译：用于开发模式触发信号的阈值检测电路包括接收输入信号的输入。响应于具有触发时间的输入阈值的输入信号，阈值检测电路在输出端激活模式触发信号。响应于输入信号基本上不同于输入阈值或不具有用于触发时间的输入阈值的输入信号，电路停用模式触发信号。阈值检测电路可以包含在各种不同的模式检测电路中，用于检测何时将集成电路放置在测试模式或其他期望的操作模式中，并且这种模式检测电路可以包含在各种不同类型的集成电路，例如一般的存储器件和SRAM。

4. 发明申请

US20060164125A1 Comparator with offset compensation 有权
标题翻译：具有偏移补偿的比较器
公开(公告)号：US20060164125A1
公开(公告)日：2006-07-27
申请号：US11038386
申请日：2005-01-21
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： G01R19/00
CPC分类号： G01R19/16519 , G01R19/16557 , H03F3/45183 , H03F3/45632 , H03F2200/78 , H03F2203/45366 , H03F2203/45644 , H03M1/0607
摘要： A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.
摘要翻译：具有减小偏移的差分比较器。差分比较器包括耦合到第一输入电流的第一晶体管和耦合到第二输入电流的第二晶体管。第一和第二晶体管在复位阶段被偏置为二极管，以便在第一和第二晶体管的寄生电容上存储偏移电压。第一和第二晶体管作为锁存器连接在一起以在锁存相位期间提供输出。第一和第二晶体管的漏极电流分别在复位阶段期间和锁存相位开始时基本上等于第一和第二输入电流。在锁存阶段期间，分别向第一和第二晶体管提供大约是由第一和第二输入电流提供的差分模式信号电流的两倍的电流。

5. 发明申请

US20050134327A1 High Speed signal level detector 有权
标题翻译：高速信号电平检测器
公开(公告)号：US20050134327A1
公开(公告)日：2005-06-23
申请号：US10743571
申请日：2003-12-22
申请人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
发明人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
IPC分类号： G01R19/165 , H03K5/153
CPC分类号： G01R19/16557
摘要： A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.
摘要翻译：高速信号电平检测器采用逆变器的高增益和高带宽进行比较。高速信号电平检测器能够实现期望的高速电平检测，而不需要使用平均技术或高带宽运算放大器型比较器所需的实质功耗。

6. 发明授权

US06700416B2 Input buffer and method for voltage level detection 有权
标题翻译：输入缓冲器和电压检测方法
公开(公告)号：US06700416B2
公开(公告)日：2004-03-02
申请号：US10371374
申请日：2003-02-19
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： H03K522
CPC分类号： H03K5/08 , G01R19/16519 , G01R19/16557 , G01R19/16595 , G01R31/30 , G01R31/31721
摘要： An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements. In addition, the input buffer can provide for multiple operations from the same die pad without requiring the addition of command pins.
摘要翻译：提供了一种改进的输入缓冲电路和配置用于电压检测的方法，其可以便于使用中级电压进行测试。配置用于电压检测的示例性输入缓冲器包括参考发生器和多状态检测器。参考发生器被配置为产生要作为输入信号提供给多状态检测器的至少两个参考电压。多状态检测器被适当地配置为接收输入参考信号，并且通过将输入参考信号与两个参考电压进行比较，将输出信号提供给表示高，低和中等级操作状态的三个输出端子。示例性输入缓冲器电路可以包括以背对背布置配置并共享公共节点的两个差分对晶体管，从而导致较低的电流要求。此外，输入缓冲器可以提供来自相同管芯焊盘的多个操作，而不需要添加命令引脚。

7. 发明授权

US4945261A Level and edge sensitive input circuit 失效
标题翻译：电平和边沿敏感输入电路
公开(公告)号：US4945261A
公开(公告)日：1990-07-31
申请号：US329236
申请日：1989-03-27
申请人： Michael E. Wright
发明人： Michael E. Wright
IPC分类号： G06F3/00 , G01R19/165 , H01H9/54 , H03K5/08
CPC分类号： G01R19/16557
摘要： A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

8. 发明授权

US4860230A Signal recognition system 失效
标题翻译：信号识别系统
公开(公告)号：US4860230A
公开(公告)日：1989-08-22
申请号：US99706
申请日：1987-09-21
申请人： Daniel Sallaerts , Michel C. A. R. Rahier
发明人： Daniel Sallaerts , Michel C. A. R. Rahier
IPC分类号： H04Q3/72 , G01R19/165 , G01R29/027 , H04M3/02 , H04M3/22
CPC分类号： G01R19/16557 , G01R29/0273
摘要： A signal persistence time interval recognition system reproduces a condition of an input signal as a condition of an output signal only when the input signal condition persists for at least a predetermined time interval. The system periodically scans the input signal condition and has a first memory (ROM) for storing a start value indicative of the time interval. A second memory (RAM) stores a value indicative of the time counted since the detection of a difference between the input and output signal conditions. A third memory stores the output signal condition and a processor brings the start value from the first memory into the second memory when no difference is detected. The processor modifies the value in the second memory each time such a difference is detected and until a value is reached indicating that the time interval has been counted, the output signal condition in the third memory being then changed. The first memory only stores a single start value for all conditions of the input signal and the processor perform the modification in the second memory independently of the first memory.
摘要翻译：信号持续时间间隔识别系统仅在输入信号条件持续至少预定的时间间隔时才将输入信号的条件再现为输出信号的条件。系统周期性地扫描输入信号条件，并具有用于存储指示时间间隔的起始值的第一存储器（ROM）。第二存储器（RAM）存储指示从检测到输入和输出信号条件之间的差值开始计数的时间的值。第三存储器存储输出信号条件，并且当没有检测到差异时，处理器将起始值从第一存储器引入第二存储器。处理器每当检测到这种差异时修改第二存储器中的值，并且直到达到指示时间间隔已被计数的值，则第三存储器中的输出信号条件随后改变。第一存储器仅存储输入信号的所有条件的单个起始值，并且处理器独立于第一存储器执行第二存储器中的修改。

9. 发明授权

US4599557A Logic probe 失效
标题翻译：逻辑探头
公开(公告)号：US4599557A
公开(公告)日：1986-07-08
申请号：US509342
申请日：1983-06-30
申请人： Victor L. Cestaro
发明人： Victor L. Cestaro
IPC分类号： G01R1/067 , G01R19/165 , G01R19/14
CPC分类号： G01R19/16557 , G01R1/06766
摘要： A test probe for determining the logic state of a digital logic circuit, which probe utilizes threshold detectors to determine the relative voltage level of a test point, and gate circuits to enable various voltage conditions, e.g., a ground, high, low, uncommitted, or a supply voltage, or a random pulse or a pulse train, to be be monitored and the test result indicated on an LED alpha display device. The threshold detectors are selectively settable so that the probe is particularly adapted to test TTL and CMOS circuitry.
摘要翻译：用于确定数字逻辑电路的逻辑状态的测试探针，该探针利用阈值检测器来确定测试点的相对电压电平，以及门电路，以实现各种电压条件，例如地，高，低，未提交，或供电电压，随机脉冲或脉冲串，并在LED alpha显示设备上指示测试结果。阈值检测器可选择性地设置，使得探头特别适用于测试TTL和CMOS电路。

10. 发明授权

US4523143A Digital logic level comparator particularly for digital test systems 失效
标题翻译：数字逻辑电平比较器特别适用于数字测试系统
公开(公告)号：US4523143A
公开(公告)日：1985-06-11
申请号：US389880
申请日：1982-06-18
申请人： Robert V. Dvorak
发明人： Robert V. Dvorak
IPC分类号： H03K5/08 , G01R19/165 , G01R31/317 , G01R31/319 , G01R31/3193 , H03K19/00
CPC分类号： G01R31/3193 , G01R19/16557 , G01R31/31703 , G01R31/31924 , G01R31/31932
摘要： A digital comparator for determining whether a digital test signal qualifies as an expected logic level, particularly suited to in-circuit digital testing applications. First and second comparing circuits, each formed by a differential amplifier circuit, receive the test signal, a high threshold signal and a low threshold signal. A control circuit selectively enables and inhibits the two comparing circuits so that only one is operative at any instant depending on the expected level of the test signal. The output terminals of the comparing circuits are connected so that the enabled one of the comparing circuits directly provides a pass/fail indication. A standby circuit allows both comparing circuits simultaneously to be selectively energized or deenergized, and an input buffer circuit permits the selective variation of the input impedance of the comparing circuit on the basis of the type of test being performed.
摘要翻译：用于确定数字测试信号是否符合期望逻辑电平的数字比较器，特别适用于在线数字测试应用。由差分放大电路形成的第一和第二比较电路接收测试信号，高阈值信号和低阈值信号。控制电路选择性地启用和禁止两个比较电路，使得根据测试信号的预期电平，只有一个在任何时刻运行。连接比较电路的输出端子，使得使能的比较电路之一直接提供通过/失败指示。备用电路允许两个比较电路同时被选择性地通电或断电，并且输入缓冲电路允许基于所执行的测试类型选择性地改变比较电路的输入阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式