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1. 发明申请

US20130337629A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130337629A1
公开(公告)日：2013-12-19
申请号：US13523912
申请日：2012-06-15
申请人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
发明人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/108 , H01L27/10861 , H01L29/945
摘要： A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
摘要翻译：描述制造半导体器件的方法。提供具有第一和第二区域的基板。第一图案化掩模层在第一区域中具有至少一个第一开口和第二区域中的至少一个第二开口形成在衬底上，其中第一开口小于第二开口。用第一图案化掩模层作为掩模去除衬底的一部分，以分别在第一和第二区域中的衬底中形成第一和第二沟槽，其中第一沟槽的宽度和深度小于第二沟槽的宽度和深度沟。至少在第一和第二沟槽中形成第一介电层。在所述第一和第二沟槽中的每一个的侧壁的至少一部分上的第一介电层上形成导电结构。

2. 发明授权

US08659079B2 Transistor device and method for manufacturing the same 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08659079B2
公开(公告)日：2014-02-25
申请号：US13481975
申请日：2012-05-29
申请人： Wei-Ming Liao , Tieh-Chiang Wu
发明人： Wei-Ming Liao , Tieh-Chiang Wu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/74 , H01L31/111
CPC分类号： H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
摘要翻译：提供了至少包括垂直晶体管结构的晶体管器件。垂直晶体管结构包括衬底，电介质层，栅极，第一掺杂区域，第二掺杂区域，第三掺杂区域和第四掺杂区域。电介质层设置在衬底的沟槽中。栅极设置在电介质层中。栅极在其两侧限定衬底中的第一沟道区和第二沟道区。第一掺杂区域和第三掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域下方。第二掺杂区域和第四掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域上方。

3. 发明申请

US20130320442A1 TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US20130320442A1
公开(公告)日：2013-12-05
申请号：US13481975
申请日：2012-05-29
申请人： Wei-Ming Liao , Tieh-Chiang Wu
发明人： Wei-Ming Liao , Tieh-Chiang Wu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
摘要翻译：提供了至少包括垂直晶体管结构的晶体管器件。垂直晶体管结构包括衬底，电介质层，栅极，第一掺杂区域，第二掺杂区域，第三掺杂区域和第四掺杂区域。电介质层设置在衬底的沟槽中。栅极设置在电介质层中。栅极在其两侧限定衬底中的第一沟道区和第二沟道区。第一掺杂区域和第三掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域下方。第二掺杂区域和第四掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域上方。

4. 发明授权

US08912065B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08912065B2
公开(公告)日：2014-12-16
申请号：US13523912
申请日：2012-06-15
申请人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
发明人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
IPC分类号： H01L21/336
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/108 , H01L27/10861 , H01L29/945
摘要： A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
摘要翻译：描述制造半导体器件的方法。提供具有第一和第二区域的基板。第一图案化掩模层在第一区域中具有至少一个第一开口和第二区域中的至少一个第二开口形成在衬底上，其中第一开口小于第二开口。用第一图案化掩模层作为掩模去除衬底的一部分，以分别在第一和第二区域中的衬底中形成第一和第二沟槽，其中第一沟槽的宽度和深度小于第二沟槽的宽度和深度沟。至少在第一和第二沟槽中形成第一电介质层。在所述第一和第二沟槽中的每一个的侧壁的至少一部分上的第一介电层上形成导电结构。

5. 发明授权

US07667262B2 Two bit U-shaped memory structure and method of making the same 有权
标题翻译：两位U形记忆体结构及制作方法
公开(公告)号：US07667262B2
公开(公告)日：2010-02-23
申请号：US12139499
申请日：2008-06-15
申请人： Wei-Ming Liao , Jer-Chyi Wang
发明人： Wei-Ming Liao , Jer-Chyi Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/1037 , H01L29/1041 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.
摘要翻译：存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

6. 发明申请

US20090075467A1 METHOD FOR MANUFACTURING A FLASH MEMORY DEVICE 有权
标题翻译：用于制造闪存存储器件的方法
公开(公告)号：US20090075467A1
公开(公告)日：2009-03-19
申请号：US12016109
申请日：2008-01-17
申请人： Wei-Ming Liao , Ming-Cheng Chang
发明人： Wei-Ming Liao , Ming-Cheng Chang
IPC分类号： H01L21/3205
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42324
摘要： A method for forming a semiconductor device includes providing a substrate and forming conductor patterns and openings on the substrate. Next the openings are filled with a mask layer and upper portions of the conductor patterns are etched to form cavities. Following, a portion of the mask layer is removed to form a trench between two neighboring conductor patterns, wherein the trench exposes the substrate and the sidewalls of the two neighboring conductor patterns. Next, an insulating layer on the cavities and the trench is conformably formed, a second conductive layer is formed on the insulating layer and the trench is filled with the second conductive layer.
摘要翻译：一种用于形成半导体器件的方法包括提供衬底并在衬底上形成导体图案和开口。接下来，开口填充有掩模层，并且蚀刻导体图案的上部以形成空腔。接下来，去除掩模层的一部分以在两个相邻导体图案之间形成沟槽，其中沟槽暴露衬底和两个相邻导体图案的侧壁。接下来，形成在空腔和沟槽上的绝缘层，在绝缘层上形成第二导电层，并且沟槽填充有第二导电层。

7. 发明授权

US08288231B1 Method of fabricating a recessed channel access transistor device 有权
标题翻译：凹陷通道存取晶体管器件的制造方法
公开(公告)号：US08288231B1
公开(公告)日：2012-10-16
申请号：US13212209
申请日：2011-08-18
申请人： Wei-Ming Liao , Ming-Cheng Chang
发明人： Wei-Ming Liao , Ming-Cheng Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/28114 , H01L29/4236 , H01L29/42376 , H01L29/4983 , H01L29/66621 , H01L29/66628
摘要： A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.
摘要翻译：提供一种制造凹槽通道存取晶体管器件的方法。首先，提供其上具有蚀刻成主表面的凹部的半导体衬底。然后在凹部的内表面上形成栅极电介质层。然后在凹部中和凹部上形成凹陷栅电极。凹陷栅电极包括凹入的栅极部分，其嵌入凹部中并在主表面下方，以及在上表面上方的上栅极部分。凹入栅电极的暴露的侧壁被各向同性地蚀刻，从而形成宽度小于凹入栅极部分的宽度的修整颈部。然后将经修整的颈部的暴露的侧壁氧化。

8. 发明申请

US20090256189A1 TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：两位U形存储器结构及其制造方法
公开(公告)号：US20090256189A1
公开(公告)日：2009-10-15
申请号：US12139499
申请日：2008-06-15
申请人： Wei-Ming Liao , Jer-Chyi Wang
发明人： Wei-Ming Liao , Jer-Chyi Wang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/1037 , H01L29/1041 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.
摘要翻译：存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

9. 发明申请

US20090085089A1 TWO-BIT FLASH MEMORY 有权
标题翻译：两位闪存
公开(公告)号：US20090085089A1
公开(公告)日：2009-04-02
申请号：US12099168
申请日：2008-04-08
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42336
摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
摘要翻译：闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。突出部从基板的顶面延伸。控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。电介质层夹在控制栅极和两个浮栅之中。由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

10. 发明申请

US20090047764A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090047764A1
公开(公告)日：2009-02-19
申请号：US11953076
申请日：2007-12-10
申请人： Wei-Ming Liao , Ming-Cheng Chang , Chien-Chang Huang
发明人： Wei-Ming Liao , Ming-Cheng Chang , Chien-Chang Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521
摘要： A non-volatile memory having a gate structure and a source/drain region is provided. The gate structure is disposed on a substrate. The gate structure includes a pair of floating gates, tunneling dielectric layers, a control gate and an inter-gate dielectric layer. The floating gates are disposed on the substrate. Each tunneling dielectric layer is disposed between each floating gate and the substrate. The control gate is disposed on the substrate between the pair of the floating gates and covers a top surface and sidewalls of each floating gate. The inter-gate dielectric layer is disposed between the control gate and each of the floating gates, disposed between the control gate and each of the tunneling dielectric layers, and disposed between the control gate and the substrate. The source/drain region is disposed in the substrate at respective sides of the gate structure.
摘要翻译：提供具有栅极结构和源极/漏极区域的非易失性存储器。栅极结构设置在基板上。栅极结构包括一对浮置栅极，隧道电介质层，控制栅极和栅极间介电层。浮置栅极设置在基板上。每个隧道介电层设置在每个浮动栅极和衬底之间。控制栅极设置在一对浮置栅极之间的衬底上并且覆盖每个浮动栅极的顶表面和侧壁。栅极间电介质层设置在控制栅极和每个浮置栅极之间，设置在控制栅极和每个隧道介电层之间，并且设置在控制栅极和衬底之间。源极/漏极区域在栅极结构的相应侧设置在衬底中。

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