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1. 发明授权

US08659079B2 Transistor device and method for manufacturing the same 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08659079B2
公开(公告)日：2014-02-25
申请号：US13481975
申请日：2012-05-29
申请人： Wei-Ming Liao , Tieh-Chiang Wu
发明人： Wei-Ming Liao , Tieh-Chiang Wu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/74 , H01L31/111
CPC分类号： H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
摘要翻译：提供了至少包括垂直晶体管结构的晶体管器件。垂直晶体管结构包括衬底，电介质层，栅极，第一掺杂区域，第二掺杂区域，第三掺杂区域和第四掺杂区域。电介质层设置在衬底的沟槽中。栅极设置在电介质层中。栅极在其两侧限定衬底中的第一沟道区和第二沟道区。第一掺杂区域和第三掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域下方。第二掺杂区域和第四掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域上方。

2. 发明申请

US20130320442A1 TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US20130320442A1
公开(公告)日：2013-12-05
申请号：US13481975
申请日：2012-05-29
申请人： Wei-Ming Liao , Tieh-Chiang Wu
发明人： Wei-Ming Liao , Tieh-Chiang Wu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
摘要翻译：提供了至少包括垂直晶体管结构的晶体管器件。垂直晶体管结构包括衬底，电介质层，栅极，第一掺杂区域，第二掺杂区域，第三掺杂区域和第四掺杂区域。电介质层设置在衬底的沟槽中。栅极设置在电介质层中。栅极在其两侧限定衬底中的第一沟道区和第二沟道区。第一掺杂区域和第三掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域下方。第二掺杂区域和第四掺杂区域分别设置在衬底中并位于第一沟道区域和第二沟道区域上方。

3. 发明申请

US20130049110A1 Vertical Transistor Devices, Memory Arrays, And Methods Of Forming Vertical Transistor Devices 有权
公开(公告)号：US20130049110A1
公开(公告)日：2013-02-28
申请号：US13215981
申请日：2011-08-23
申请人： Kuo Chen Wang , Sriraj Manavalan , Wei Ming Liao
发明人： Kuo Chen Wang , Sriraj Manavalan , Wei Ming Liao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L29/66666 , H01L29/7827
摘要： A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

4. 发明申请

US20090267126A1 RECESS CHANNEL TRANSISTOR 审中-公开
标题翻译：录音通道晶体管
公开(公告)号：US20090267126A1
公开(公告)日：2009-10-29
申请号：US12141070
申请日：2008-06-17
申请人： Jer-Chyi Wang , Wei-Ming Liao
发明人： Jer-Chyi Wang , Wei-Ming Liao
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L27/10823
摘要： A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction.
摘要翻译：凹槽通道晶体管包括半导体衬底; 半导体衬底中的沟槽隔离区域，其限定有源区域; 所述有源区中的栅极沟槽，其中所述栅极沟槽包括圆形下部; 嵌入栅极沟槽中的凹入栅极，其具有位于圆形下部中的球形栅极部分; 在半导体衬底和球形栅极部分之间的圆形下部中的栅氧化层; 在所述凹入栅极的一侧的有源区域中的源极区域; 在所述凹入栅极的另一侧的所述有源区域中的漏极区域; 以及源极区域和漏极区域之间的沟道区域，其中当从沟道宽度方向观察时，沟道区域呈现凸曲线轮廓。

5. 发明申请

US20090108321A1 FLASH MEMORY 审中-公开
标题翻译：闪存
公开(公告)号：US20090108321A1
公开(公告)日：2009-04-30
申请号：US11948947
申请日：2007-11-30
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , H01L29/40114 , H01L29/42324 , H01L29/7887
摘要： A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate.
摘要翻译：提供闪存。闪速存储器包括基板，形成在基板上的第一绝缘层，设置在第一绝缘层上的控制栅极和与分别设置在控制栅极两侧的基板共面的两个浮动栅极。

6. 发明申请

US20080265342A1 TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：双位闪存存储器单元及其制造方法
公开(公告)号：US20080265342A1
公开(公告)日：2008-10-30
申请号：US11780482
申请日：2007-07-20
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Chien-Chang Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7923 , H01L29/40117 , H01L29/42348
摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.
摘要翻译：两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，栅极氧化物层上的T形栅极。第一电荷存储层设置在T形门的一侧和下方。通过T形栅极和栅极氧化物层的底部与第一电荷存储层分离的第二电荷存储层设置在T形栅极的另一侧和下方。绝缘层设置在T形栅极和栅极氧化物层之间。第一源极/漏极区域设置在衬底内的T形栅极的一侧。第二源极/漏极区域设置在衬底内的T形栅极的另一侧。

7. 发明授权

US09401363B2 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices 有权
标题翻译：垂直晶体管器件，存储器阵列和形成垂直晶体管器件的方法
公开(公告)号：US09401363B2
公开(公告)日：2016-07-26
申请号：US13215981
申请日：2011-08-23
申请人： Kuo Chen Wang , Sriraj Manavalan , Wei Ming Liao
发明人： Kuo Chen Wang , Sriraj Manavalan , Wei Ming Liao
IPC分类号： H01L21/8239 , H01L27/108 , H01L29/66 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L29/66666 , H01L29/7827
摘要： A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.
摘要翻译：垂直晶体管器件包括与绝缘隔离线相邻的有源区线。掩埋数据/感测线相对于有源区线和介质隔离线倾斜地倾斜。一对栅极线位于掩埋数据/感测线之外，并且相对于有源区线和介电隔离线的倾斜角度。垂直晶体管沟道区域在该对栅极线之间的有效区域内。外部源极/漏极区域在沟道区域上方的有源区域中，并且内部源极/漏极区域在沟道区域下方的有源区域中。内部源极/漏极区域电耦合到掩埋的数据/感测线。考虑形成多个垂直晶体管器件的方法也考虑了其它器件和结构。

8. 发明授权

US08288231B1 Method of fabricating a recessed channel access transistor device 有权
标题翻译：凹陷通道存取晶体管器件的制造方法
公开(公告)号：US08288231B1
公开(公告)日：2012-10-16
申请号：US13212209
申请日：2011-08-18
申请人： Wei-Ming Liao , Ming-Cheng Chang
发明人： Wei-Ming Liao , Ming-Cheng Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/28114 , H01L29/4236 , H01L29/42376 , H01L29/4983 , H01L29/66621 , H01L29/66628
摘要： A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.
摘要翻译：提供一种制造凹槽通道存取晶体管器件的方法。首先，提供其上具有蚀刻成主表面的凹部的半导体衬底。然后在凹部的内表面上形成栅极电介质层。然后在凹部中和凹部上形成凹陷栅电极。凹陷栅电极包括凹入的栅极部分，其嵌入凹部中并在主表面下方，以及在上表面上方的上栅极部分。凹入栅电极的暴露的侧壁被各向同性地蚀刻，从而形成宽度小于凹入栅极部分的宽度的修整颈部。然后将经修整的颈部的暴露的侧壁氧化。

9. 发明申请

US20090256189A1 TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：两位U形存储器结构及其制造方法
公开(公告)号：US20090256189A1
公开(公告)日：2009-10-15
申请号：US12139499
申请日：2008-06-15
申请人： Wei-Ming Liao , Jer-Chyi Wang
发明人： Wei-Ming Liao , Jer-Chyi Wang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/1037 , H01L29/1041 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.
摘要翻译：存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

10. 发明申请

US20090085089A1 TWO-BIT FLASH MEMORY 有权
标题翻译：两位闪存
公开(公告)号：US20090085089A1
公开(公告)日：2009-04-02
申请号：US12099168
申请日：2008-04-08
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42336
摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
摘要翻译：闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。突出部从基板的顶面延伸。控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。电介质层夹在控制栅极和两个浮栅之中。由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

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