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1. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

2. 发明申请

US20120327704A1 SEMICONDUCTOR MEMORIES 有权
标题翻译：半导体记忆
公开(公告)号：US20120327704A1
公开(公告)日：2012-12-27
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

3. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

4. 发明申请

US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于在半导体器件中形成器件电池的布局方案和方法
公开(公告)号：US20120256235A1
公开(公告)日：2012-10-11
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

5. 发明申请

US20100157692A1 Distributed VDC for SRAM Memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US20100157692A1
公开(公告)日：2010-06-24
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

6. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

7. 发明申请

US20110199847A1 SENSE AMPLIFIER WITH LOW SENSING MARGIN AND HIGH DEVICE VARIATION TOLERANCE 有权
标题翻译：具有低感测尺寸和高设备变化公差的感测放大器
公开(公告)号：US20110199847A1
公开(公告)日：2011-08-18
申请号：US12708108
申请日：2010-02-18
申请人： Yen-Huei CHEN , Hsien-Yu Pan , Shao-Yu Chou
发明人： Yen-Huei CHEN , Hsien-Yu Pan , Shao-Yu Chou
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/005
摘要： In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.
摘要翻译：在与感测放大器相关的实施例中，读出放大器包括一对晶体管（例如，晶体管P2和P3），其适当时使得能够将输入线DL和DLB上的数据直接预设到内部节点（例如，节点 S和SB），从中读出数据。此外，这对晶体管P2和P3也允许内部节点S和SB共享线DL和DLB的预充电机制。

8. 发明授权

US08570823B2 Sense amplifier with low sensing margin and high device variation tolerance 有权
标题翻译：感测放大器具有低感测裕度和高器件变化公差
公开(公告)号：US08570823B2
公开(公告)日：2013-10-29
申请号：US12708108
申请日：2010-02-18
申请人： Yen-Huei Chen , Hsien-Yu Pan , Shao-Yu Chou
发明人： Yen-Huei Chen , Hsien-Yu Pan , Shao-Yu Chou
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/005
摘要： In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.
摘要翻译：在与感测放大器相关的实施例中，读出放大器包括一对晶体管（例如，晶体管P2和P3），其适当时使得能够将输入线DL和DLB上的数据直接预设到内部节点（例如，节点 S和SB），从中读出数据。此外，这对晶体管P2和P3也允许内部节点S和SB共享线DL和DLB的预充电机制。

9. 发明申请

US20070133275A1 Low-power reading reference circuit for split-gate flash memory 审中-公开
标题翻译：分闸式闪存的低功耗读取参考电路
公开(公告)号：US20070133275A1
公开(公告)日：2007-06-14
申请号：US11473250
申请日：2006-06-22
申请人： Meng-Fan Chang , Hsien-Yu Pan , Ding-Ming Kwai , Yung-Fa Chou
发明人： Meng-Fan Chang , Hsien-Yu Pan , Ding-Ming Kwai , Yung-Fa Chou
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , H01L27/115
摘要： A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.
摘要翻译：用于分闸器闪速存储器的低功率读取参考电路至少包括一对第一参考单元和第二参考单元，其向分闸器闪存的常规单元提供读取参考电流。第一参考单元的第一浮动栅极和第二参考单元的第二浮置栅极连接到逻辑电路的输出。逻辑电路接收至少一个外部状态信号以确定分闸器闪存是否准备好切换到读取模式，然后在激活和去激活的状态之间切换第一浮动栅极和第二浮动栅极，因此以激活第一参考单元或第二参考单元以提供参考电流。

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