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1. 发明申请

US20070133275A1 Low-power reading reference circuit for split-gate flash memory 审中-公开
标题翻译：分闸式闪存的低功耗读取参考电路
公开(公告)号：US20070133275A1
公开(公告)日：2007-06-14
申请号：US11473250
申请日：2006-06-22
申请人： Meng-Fan Chang , Hsien-Yu Pan , Ding-Ming Kwai , Yung-Fa Chou
发明人： Meng-Fan Chang , Hsien-Yu Pan , Ding-Ming Kwai , Yung-Fa Chou
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , H01L27/115
摘要： A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.
摘要翻译：用于分闸器闪速存储器的低功率读取参考电路至少包括一对第一参考单元和第二参考单元，其向分闸器闪存的常规单元提供读取参考电流。第一参考单元的第一浮动栅极和第二参考单元的第二浮置栅极连接到逻辑电路的输出。逻辑电路接收至少一个外部状态信号以确定分闸器闪存是否准备好切换到读取模式，然后在激活和去激活的状态之间切换第一浮动栅极和第二浮动栅极，因此以激活第一参考单元或第二参考单元以提供参考电流。

2. 发明授权

US08912015B2 Operating method of hardwired switch 有权
标题翻译：硬连线开关的操作方法
公开(公告)号：US08912015B2
公开(公告)日：2014-12-16
申请号：US13477057
申请日：2012-05-22
申请人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
发明人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H01L21/66 , H01L23/525 , H01L23/48 , H01L25/065
CPC分类号： H01L23/525 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.
摘要翻译：提供了一种硬连线开关的操作方法。首先，提供第一个模具。第一个裸片配置为硬连线开关中的第一个裸片。接下来，检查第一管芯的功能以获得检查结果。在检查结果中，第二TSV是否选择性地设置在第一着陆垫和第五着陆垫之间，在第二着陆垫和第六着陆垫之间，第三着陆垫和第七着陆垫之间，或在第四着陆垫之间垫和第八着陆垫是否被确定。第一模具堆叠在第二模具上方，使得第二表面位于第一模具和第二模具之间。

3. 发明申请

US20130064026A1 TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
标题翻译：三维集成电路堆叠后记忆修复技术
公开(公告)号：US20130064026A1
公开(公告)日：2013-03-14
申请号：US13294181
申请日：2011-11-11
申请人： Yung-Fa Chou , Ding-Ming Kwai
发明人： Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/785
摘要： A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked.
摘要翻译：三维集成电路（3-D IC）包括控制器芯片和至少一个存储器芯片，其中，除了原始存储容量之外，存储芯片还包括多个备用存储器单元和具有外部激活的地址转换电路 /启用功能。在存储器芯片和控制器芯片堆叠之后，控制器芯片仍然可以通过至少一个垂直互连（例如，通过硅片）来激活/启用存储器芯片中的备用器件来修复存储器芯片中的损坏或恶化的存储器单元通过（TSV）），无论在控制器芯片和存储芯片堆叠之前，是否已经修复了损坏或变坏的存储单元。

4. 发明授权

US08384201B2 Wafer and method for improving yield rate of wafer 有权
标题翻译：晶圆和提高晶圆产率的方法
公开(公告)号：US08384201B2
公开(公告)日：2013-02-26
申请号：US12566632
申请日：2009-09-24
申请人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
发明人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H01L23/02
CPC分类号： H01L23/5252 , H01L22/22 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.
摘要翻译：提供晶片和提高晶片的屈服率的方法。晶片包括第一和第二电路单元，第一和第二通孔硅通孔（TSV）和第一备用TSV。第一和第二电路单元设置在晶片内。第一TSV垂直穿过晶片，并通过晶片的前金属耦合到第一电路单元。第二TSV垂直穿过晶片，并通过晶片的前金属耦合到第二电路单元。当第一或第二TSV失效时，第一备用TSV垂直通过晶片以替换故障的第一或第二TSV。

5. 发明申请

US20100244220A1 LAYOUT STRUCTURE AND METHOD OF DIE 有权
标题翻译：布置结构和方法
公开(公告)号：US20100244220A1
公开(公告)日：2010-09-30
申请号：US12484250
申请日：2009-06-15
申请人： Yung-Fa Chou , Ding-Ming Kwai
发明人： Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2224/05552
摘要： A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.
摘要翻译：提供了布局结构和布局方法。布局结构包括第一导电通孔，第二导电通孔，管芯和八个焊盘。第一导电通孔和第二导电通孔穿过管芯。第一导电通孔具有第一焊盘和第二焊盘，并且第二导电通孔具有第三焊盘和第四焊盘。向第三垫进行第五垫。向第二垫进行第六垫。向第一垫进行第七垫。向第四垫进行第八垫。在芯片的垂直方向上，第一焊盘和第二焊盘重叠，第三焊盘和第四焊盘重叠，第五焊盘和第六焊盘重叠，第八焊盘和第七焊盘重叠，部分或完全。

6. 发明授权

US09048342B2 Semiconductor device stacked structure 有权
标题翻译：半导体器件堆叠结构
公开(公告)号：US09048342B2
公开(公告)日：2015-06-02
申请号：US13450482
申请日：2012-04-19
申请人： Ding-Ming Kwai , Yung-Fa Chou , Chiao-Ling Lung , Jui-Hung Chien
发明人： Ding-Ming Kwai , Yung-Fa Chou , Chiao-Ling Lung , Jui-Hung Chien
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L25/065 , H01L23/58
CPC分类号： H01L24/94 , H01L23/481 , H01L23/562 , H01L23/585 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/1301 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1316 , H01L2224/13184 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2924/10253 , H01L2924/3511 , H01L2224/81 , H01L2924/00
摘要： A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.
摘要翻译：公开了一种半导体器件堆叠结构，其包括多个半导体器件和至少一个加强结构。半导体器件彼此堆叠。至少一个半导体器件具有至少一个通硅通孔。每个加强结构围绕至少一个通过硅通孔中的对应的一个，并且与半导体器件电绝缘。至少一个加强结构包括多个加强元件和至少一个连接元件。每个加强元件设置在半导体器件之间。平面上的加强元件的垂直突起限定了紧密的区域，并且该平面上的至少一个穿过硅通孔的突出部位于紧密区域内。连接元件位于平面上的加强元件的垂直突起的重叠区域中，用于连接加强元件以形成加强结构。

7. 发明申请

US20130161819A1 SEMICONDUCTOR DEVICE STACKED STRUCTURE 有权
标题翻译：半导体器件堆叠结构
公开(公告)号：US20130161819A1
公开(公告)日：2013-06-27
申请号：US13450482
申请日：2012-04-19
申请人： Ding-Ming Kwai , Yung-Fa Chou , Chiao-Ling Lung , Jui-Hung Chien
发明人： Ding-Ming Kwai , Yung-Fa Chou , Chiao-Ling Lung , Jui-Hung Chien
IPC分类号： H01L23/48
CPC分类号： H01L24/94 , H01L23/481 , H01L23/562 , H01L23/585 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/1301 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1316 , H01L2224/13184 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2924/10253 , H01L2924/3511 , H01L2224/81 , H01L2924/00
摘要： A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.
摘要翻译：公开了一种半导体器件堆叠结构，其包括多个半导体器件和至少一个加强结构。半导体器件彼此堆叠。至少一个半导体器件具有至少一个通硅通孔。每个加强结构围绕至少一个通过硅通孔中的对应的一个，并且与半导体器件电绝缘。至少一个加强结构包括多个加强元件和至少一个连接元件。每个加强元件设置在半导体器件之间。平面上的加强元件的垂直突起限定了紧密的区域，并且该平面上的至少一个穿过硅通孔的突出部位于紧密区域内。连接元件位于平面上的加强元件的垂直突起的重叠区域中，用于连接加强元件以形成加强结构。

8. 发明申请

US20120231563A1 OPERATING METHOD OF HARDWIRED SWITCH 审中-公开
标题翻译：硬开关的操作方法
公开(公告)号：US20120231563A1
公开(公告)日：2012-09-13
申请号：US13477057
申请日：2012-05-22
申请人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
发明人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H01L21/66
CPC分类号： H01L23/525 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.
摘要翻译：提供了一种硬连线开关的操作方法。首先，提供第一个模具。第一个裸片配置为硬连线开关中的第一个裸片。接下来，检查第一管芯的功能以获得检查结果。在检查结果中，第二TSV是否选择性地设置在第一着陆垫和第五着陆垫之间，在第二着陆垫和第六着陆垫之间，第三着陆垫和第七着陆垫之间，或在第四着陆垫之间垫和第八着陆垫是否被确定。第一模具堆叠在第二模具上方，使得第二表面位于第一模具和第二模具之间。

9. 发明授权

US07924083B2 Isolation circuit 有权
标题翻译：隔离电路
公开(公告)号：US07924083B2
公开(公告)日：2011-04-12
申请号：US12551551
申请日：2009-08-31
申请人： Yung-Fa Chou , Ding-Ming Kwai
发明人： Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H03K17/16
CPC分类号： H03K17/063 , H03K17/6871 , H03K2017/066 , H03K2217/0018
摘要： An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.
摘要翻译：提供隔离电路。隔离电路耦合到输出和输入节点，并且包括第一组，第二开关组和体偏置电压发生器。当第一电压处于第一电压电平时，第一开关组将开关控制节点耦合到第二电压，并且当第一电压处于第二电压电平时将开关控制节点耦合到输入节点。当第一电压处于第一电压电平时，第二开关组将输出节点耦合到输入节点，并且当第一电压处于第二电压电平时，将输出节点与输入节点隔离。身体偏置电压发生器选择性地将输入节点上的第一电压和电压中的较高的一个提供给第二开关组的主体。

10. 发明申请

US20100320565A1 WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER 有权
标题翻译：用于改善波浪的屈服速率的方法和方法
公开(公告)号：US20100320565A1
公开(公告)日：2010-12-23
申请号：US12566632
申请日：2009-09-24
申请人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
发明人： Ting-Sheng Chen , Yung-Fa Chou , Ding-Ming Kwai
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L22/22 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.
摘要翻译：提供晶片和提高晶片的屈服率的方法。晶片包括第一和第二电路单元，第一和第二通孔硅通孔（TSV）和第一备用TSV。第一和第二电路单元设置在晶片内。第一TSV垂直穿过晶片，并通过晶片的前金属耦合到第一电路单元。第二TSV垂直穿过晶片，并通过晶片的前金属耦合到第二电路单元。当第一或第二TSV失效时，第一备用TSV垂直通过晶片以替换故障的第一或第二TSV。

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