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1. 发明授权

US07249215B2 System for configuring parameters for a flash memory 有权
公开(公告)号：US07249215B2
公开(公告)日：2007-07-24
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.

2. 发明申请

US20060253644A1 Method and system for configuring parameters for flash memory 有权
标题翻译：闪存配置参数的方法和系统
公开(公告)号：US20060253644A1
公开(公告)日：2006-11-09
申请号：US11272206
申请日：2005-11-10
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.
摘要翻译：用于配置闪存设备中使用的参数的方法和系统。从只读存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。在另一方面，如果测试的闪速存储器操作不在期望的规格内，则不存储在ROM中的一个或多个选择的配置值被改变。

3. 发明申请

US20070083699A1 System for configuring parameters for a flash memory 有权
标题翻译：用于配置闪存的参数的系统
公开(公告)号：US20070083699A1
公开(公告)日：2007-04-12
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.
摘要翻译：用于配置闪存设备中使用的参数的系统。从存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。

4. 发明授权

US07181565B2 Method and system for configuring parameters for flash memory 有权
标题翻译：闪存配置参数的方法和系统
公开(公告)号：US07181565B2
公开(公告)日：2007-02-20
申请号：US11272206
申请日：2005-11-10
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.
摘要翻译：用于配置闪存设备中使用的参数的方法和系统。从只读存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。在另一方面，如果测试的闪速存储器操作不在期望的规格内，则不存储在ROM中的一个或多个选择的配置值被改变。

5. 发明授权

US07505326B2 Programming pulse generator 有权
标题翻译：编程脉冲发生器
公开(公告)号：US07505326B2
公开(公告)日：2009-03-17
申请号：US11554829
申请日：2006-10-31
申请人： Stefano Sivero , Mirella Marsella , Mauro Chinosi , Giorgio Bosisio
发明人： Stefano Sivero , Mirella Marsella , Mauro Chinosi , Giorgio Bosisio
IPC分类号： G11C11/34
CPC分类号： G11C16/12
摘要： A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.
摘要翻译：信号发生器电路被配置为产生用于存储器阵列的程序信号。程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

6. 发明申请

US20080101124A1 PROGRAMMING PULSE GENERATOR 有权
标题翻译：编程脉冲发生器
公开(公告)号：US20080101124A1
公开(公告)日：2008-05-01
申请号：US11554829
申请日：2006-10-31
申请人： Stefano Sivero , Mirella Marsella , Mauro Chinosi , Giorgio Bosisio
发明人： Stefano Sivero , Mirella Marsella , Mauro Chinosi , Giorgio Bosisio
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.
摘要翻译：信号发生器电路被配置为产生用于存储器阵列的程序信号。程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

7. 发明授权

US07561485B2 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US07561485B2
公开(公告)日：2009-07-14
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C7/02
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

8. 发明申请

US20080170441A1 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US20080170441A1
公开(公告)日：2008-07-17
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

9. 发明授权

US07176750B2 Method and apparatus for fast power-on of the band-gap reference 有权
标题翻译：带隙基准快速上电的方法和装置
公开(公告)号：US07176750B2
公开(公告)日：2007-02-13
申请号：US11124871
申请日：2005-05-09
申请人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
发明人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.
摘要翻译：快速上电带隙参考电路包括缓冲器，第一带隙逻辑和第二高驱动带隙逻辑。在带隙参考电路的上电期间，第一带隙逻辑和第二高驱动带隙逻辑都被激活，其中第一带隙逻辑对第一带隙逻辑的输出进行充电，第二高驱动带隙逻辑对与带隙基准电路的输出相关联的电容进行充电。当第一带隙逻辑的输出达到预定值时，第二高驱动带隙逻辑被去激活，并且第一带隙逻辑的输出通过缓冲器耦合到带隙参考电路的输出。

10. 发明申请

US20060038609A1 Method and apparatus for fast power-on of the band-gap reference 有权
标题翻译：带隙基准快速上电的方法和装置
公开(公告)号：US20060038609A1
公开(公告)日：2006-02-23
申请号：US11124871
申请日：2005-05-09
申请人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
发明人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A fast power-on band-gap reference circuit includes a band-gap logic and a band-gap dummy logic. During power-on, both the band-gap logic and the band-gap dummy logic are activated and charges the capacitance of a band-gap line. When an output of the band-gap logic reaches a predetermined value, the band-gap dummy logic is deactivated. Thus, the band-gap dummy logic, with a high drive capability, charges the band-gap capacitance at the same time the band-gap logic starts to generate the compensate temperature voltage. In this manner, the band-gap reference circuit reaches its stable, functional state faster than conventional circuits, in the range of a few microseconds.
摘要翻译：快速上电带隙参考电路包括带隙逻辑和带隙虚拟逻辑。在上电期间，带隙逻辑和带隙虚拟逻辑都被激活并对带隙线的电容进行充电。当带隙逻辑的输出达到预定值时，带隙虚拟逻辑被去激活。因此，具有高驱动能力的带隙虚拟逻辑在带隙逻辑开始产生补偿温度电压的同时对带隙电容进行充电。以这种方式，带隙参考电路在几微秒的范围内达到其比常规电路更稳定的功能状态。

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