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    • 7. 发明申请
    • Detection system including avalanche photodiode for use in harsh environments
    • 检测系统包括用于恶劣环境的雪崩光电二极管
    • US20050098844A1
    • 2005-05-12
    • US10994980
    • 2004-11-19
    • Peter SandvikDale BrownStephen ArthurKevin MatochaJames Kretchmer
    • Peter SandvikDale BrownStephen ArthurKevin MatochaJames Kretchmer
    • G01J1/02H01J20060101H01L31/0232H01L31/0248H01L31/0304H01L31/0312H01L31/0352H01L31/06H01L31/062H01L31/107H01L31/113H01L31/115
    • H01L31/02322H01L31/02161H01L31/03044H01L31/0312H01L31/035281H01L31/107H01L31/115
    • An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials. According to an embodiment of the present invention, an avalanche photodiode for detecting ultraviolet photons comprises a substrate having a first dopant; a first layer having the first dopant, positioned on top of the substrate; a second layer having a second dopant, positioned on top of the first layer; a third layer having a second dopant, positioned on top of the second layer; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned on top of the third layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the third layer; wherein the avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape; and wherein the avalanche photodiode operates in an environment comprising a temperature approximately equal to 150 degrees Celsius.
    • 本发明的一个方面涉及一种雪崩光电二极管(APD)装置,用于在冲击水平接近250重力加速度(G)和/或温度接近或超过150°的恶劣的井下环境中的油井钻井应用 C.本发明的另一方面涉及使用SiC材料制造的APD器件。 本发明的另一方面涉及使用GaN材料制造的APD器件。 根据本发明的实施例,用于检测紫外光子的雪崩光电二极管包括具有第一掺杂剂的衬底; 具有第一掺杂剂的第一层,位于衬底的顶部; 具有位于所述第一层的顶部上的具有第二掺杂剂的第二层; 具有第二掺杂剂的第三层,位于所述第二层的顶部; 用于在雪崩光电二极管的表面上提供电钝化的钝化层; 用于限制移动离子迁移的磷硅酸盐玻璃层,位于第三层的顶部; 以及用于提供欧姆接触的一对金属电极,其中第一电极位于所述衬底下方,并且第二电极位于所述第三层之上; 其中所述雪崩光电二极管包括形成倾斜台面形状的第一侧壁和第二侧壁; 并且其中所述雪崩光电二极管在包括大约等于150摄氏度的温度的环境中操作。
    • 8. 发明授权
    • Silicon-carbide MOSFET cell structure and method for forming same
    • 碳化硅MOSFET单元结构及其形成方法
    • US08377756B1
    • 2013-02-19
    • US13190723
    • 2011-07-26
    • Stephen Daley ArthurKevin MatochaPeter SandvikZachary StumPeter LoseeJames McMahon
    • Stephen Daley ArthurKevin MatochaPeter SandvikZachary StumPeter LoseeJames McMahon
    • H01L29/10H01L29/76
    • H01L27/088H01L29/0696H01L29/1608H01L29/66068H01L29/7802
    • In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    • 在一个实施例中,本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在孔内的U形孔(228)(P型)和两个平行源(260)(N型)。 多个源极(262)(掺杂N)在多个位置连接源极(260)。 两个梯级(262)之间的区域包括主体(252)(P型)。 这些特征形成在形成在N型衬底(216)上的N型外延层(220)上。 接触件(290)跨越并接触多个源极(262)和主体(252)。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路,响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。