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1. 发明授权

US07545176B2 Energy-saving circuit and method using charge equalization across complementary nodes 失效
标题翻译：节能电路和方法在互补节点上使用电荷均衡
公开(公告)号：US07545176B2
公开(公告)日：2009-06-09
申请号：US11923714
申请日：2007-10-25
申请人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
发明人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K5/151 , H03K19/0008
摘要： An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
摘要翻译：在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗，例如具有互补高电容节点的宽多路复用器。改变检测电路检测要施加到位线的状态变化，并且如果要施加状态改变则产生脉冲。连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。驱动电路使能输入也被延迟，使得位线不被驱动，直到电荷被均衡并且通路禁止。在一个实施例中，驱动器电路仅通过变化检测器的脉冲输出暂时使能，并且使用保持器电路将位线保持在其断言状态。

2. 发明申请

US20090108920A1 ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES 失效
标题翻译：节能电路和使用充电均衡的方法
公开(公告)号：US20090108920A1
公开(公告)日：2009-04-30
申请号：US11923714
申请日：2007-10-25
申请人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
发明人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
IPC分类号： G05F1/10
CPC分类号： H03K5/151 , H03K19/0008
摘要： An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
摘要翻译：在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗，例如具有互补高电容节点的宽多路复用器。改变检测电路检测要施加到位线的状态变化，并且如果要施加状态改变则产生脉冲。连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。驱动电路使能输入也被延迟，使得位线不被驱动，直到电荷被均衡并且通路禁止。在一个实施例中，驱动器电路仅通过变化检测器的脉冲输出暂时使能，并且使用保持器电路将位线保持在其断言状态。

3. 发明申请

US20080251888A1 Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits 失效
标题翻译：集成电路中自包含自动去耦电容开关的方法和装置
公开(公告)号：US20080251888A1
公开(公告)日：2008-10-16
申请号：US11733435
申请日：2007-04-10
申请人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
发明人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
IPC分类号： H01L27/02
CPC分类号： H01L27/0805 , G06F1/26 , H01L27/0629 , Y10T307/865
摘要： An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.
摘要翻译：集成电路（IC）包括耦合到电源的电源互连。集成电路包括执行所需功能的电子器件，还包括在整个集成电路中提供降噪的去耦电容器电路。在一个实施例中，每个去耦电容器电路包括去耦电容器和开关电路。当开关电路检测到没有实质的去耦电容器泄漏时，开关电路在连接模式期间将去耦电容器连接到电源互连。然而，当开关电路检测到实质的去耦电容器泄漏时，开关电路在断开模式期间有效地将去耦电容器与电源互连件断开。去耦电容电路在连接模式下自我初始化，无需外部控制信号，因此是独立的。由于去耦电容电路的自包含性质，集成电路可能包含一个去耦电容电路的阵列，而不需要相应的去耦电容器控制线的大量芯片空间。

4. 发明授权

US07750511B2 Method and apparatus for self-contained automatic decoupling capacitor switch-out in integrated circuits 失效
标题翻译：集成电路中独立自动去耦电容开关的方法和装置
公开(公告)号：US07750511B2
公开(公告)日：2010-07-06
申请号：US11733435
申请日：2007-04-10
申请人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
发明人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
IPC分类号： H02H3/00
CPC分类号： H01L27/0805 , G06F1/26 , H01L27/0629 , Y10T307/865
摘要： An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.
摘要翻译：集成电路（IC）包括耦合到电源的电源互连。集成电路包括执行所需功能的电子器件，还包括在整个集成电路中提供降噪的去耦电容器电路。在一个实施例中，每个解耦电容器电路包括去耦电容器和开关电路。当开关电路检测到没有实质的去耦电容器泄漏时，开关电路在连接模式期间将去耦电容器连接到电源互连。然而，当开关电路检测到实质的去耦电容器泄漏时，开关电路在断开模式期间有效地将去耦电容器与电源互连件断开。去耦电容电路在连接模式下自我初始化，无需外部控制信号，因此是独立的。由于去耦电容电路的自包含性质，集成电路可能包含一个去耦电容电路的阵列，而不需要相应的去耦电容器控制线的大量芯片空间。

5. 发明申请

US20090010077A1 SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL 有权
标题翻译：具有嵌入式动态随机存取存储器扫描的移位寄存器
公开(公告)号：US20090010077A1
公开(公告)日：2009-01-08
申请号：US11772592
申请日：2007-07-02
申请人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
发明人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译：混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。

6. 发明授权

US07474574B1 Shift register latch with embedded dynamic random access memory scan only cell 有权
标题翻译：移位寄存器锁存器与嵌入式动态随机存取存储器扫描单元格
公开(公告)号：US07474574B1
公开(公告)日：2009-01-06
申请号：US11772592
申请日：2007-07-02
申请人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
发明人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译：混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。

7. 发明授权

US08127116B2 Dependency matrix with reduced area and power consumption 失效
标题翻译：具有减少面积和功耗的依赖矩阵
公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

8. 发明授权

US07243209B2 Apparatus and method for speeding up access time of a large register file with wrap capability 有权
标题翻译：用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法
公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
申请人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Jafar Nahidi , Dung Quoc Nguyen
发明人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Jafar Nahidi , Dung Quoc Nguyen
IPC分类号： G06F9/34 , G06F13/00
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译：提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列，需要包装能力。这些附加的主多路复用器接收读地址和移位的读字线信号。另一个主复用器接收读地址和未移位的读字线信号。来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址系统。

9. 发明申请

US20090251974A1 MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME 有权
标题翻译：具有降低漏电功率的存储器电路和相同的设计结构
公开(公告)号：US20090251974A1
公开(公告)日：2009-10-08
申请号：US12098764
申请日：2008-04-07
申请人： Sam Gat-Shang Chu , Saiful Islam , Jae-Joon Kim , Stephen V. Kosonocky
发明人： Sam Gat-Shang Chu , Saiful Islam , Jae-Joon Kim , Stephen V. Kosonocky
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C7/18 , G11C7/12 , G11C11/413 , G11C2207/2227
摘要： A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.
摘要翻译：存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。本地读位线与本地写位线分离。本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线。全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。还包括所述类型的电路的设计结构。

10. 发明申请

US20080279015A1 REGISTER FILE 有权
标题翻译：注册文件
公开(公告)号：US20080279015A1
公开(公告)日：2008-11-13
申请号：US12180520
申请日：2008-07-26
申请人： Sam Gat-Shang Chu , Saiful Islam , Shelton Siuwah Leung , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Saiful Islam , Shelton Siuwah Leung , Jose Angel Paredes
IPC分类号： G11C7/10
CPC分类号： G06F9/30141
摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.
摘要翻译：集成电路中经常使用寄存器文件来临时保存数据。有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。然而，多路复用器插入在高性能集成电路中不期望的延迟。多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。

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