专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080219063A1 SYSTEM AND METHOD OF SELECTIVE ROW ENERGIZATION BASED ON WRITE DATA 失效
标题翻译：基于写数据选择能量的系统和方法
公开(公告)号：US20080219063A1
公开(公告)日：2008-09-11
申请号：US12125875
申请日：2008-05-22
申请人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
发明人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/10
摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
摘要翻译：一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及响应于M行104中的每一个的均匀字数据位的M位行驱动器设备116，以禁止均匀字数据位为第一值的M行104的通电。

2. 发明授权

US07379348B2 System and method of selective row energization based on write data 失效
标题翻译：基于写入数据的选择性行激励的系统和方法
公开(公告)号：US07379348B2
公开(公告)日：2008-05-27
申请号：US11340535
申请日：2006-01-26
申请人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
发明人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
IPC分类号： G11C7/00
CPC分类号： G11C8/10
摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
摘要翻译：一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及响应于M行104中的每一个的均匀字数据位的M位行驱动器设备116，以禁止均匀字数据位为第一值的M行104的通电。

3. 发明申请

US20100257336A1 Dependency Matrix with Reduced Area and Power Consumption 失效
标题翻译：具有减小面积和功耗的依赖矩阵
公开(公告)号：US20100257336A1
公开(公告)日：2010-10-07
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/44 , G06F15/00 , G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

4. 发明申请

US20080123437A1 Apparatus for Floating Bitlines in Static Random Access Memory Arrays 审中-公开
标题翻译：静态随机存取存储器阵列中浮动位线的装置
公开(公告)号：US20080123437A1
公开(公告)日：2008-05-29
申请号：US11564697
申请日：2006-11-29
申请人： Vikas Agarwal , Sam G. Chu , Jose A. Paredes
发明人： Vikas Agarwal , Sam G. Chu , Jose A. Paredes
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/1012 , G11C7/1051 , G11C7/18 , G11C11/413
摘要： An apparatus for floating read bitlines of a static random access memory (SRAM) is disclosed. The SRAM includes a first and second SRAM cell columns, a first and second read bitlines, and a multiplexor. The multiplexor is coupled to the first and second SRAM cell columns via the first and second read bitlines, respectively. The multiplexor is capable of selectively transmitting data from the first or second SRAM cell column via the first or second read bitline, respectively, to an output. In addition, the multiplexor allows the first read bitline and/or the second read bitline to remain uncharged when no data are being read from the first SRAM cell column and/or the second SRAM cell column.
摘要翻译：公开了一种用于浮动读取静态随机存取存储器（SRAM）的位线的装置。 SRAM包括第一和第二SRAM单元列，第一和第二读位线以及多路复用器。多路复用器分别经由第一和第二读取位线耦合到第一和第二SRAM单元列。复用器能够分别经由第一或第二读取位线从第一或第二SRAM单元列选择性地发送数据到输出。此外，当没有从第一SRAM单元列和/或第二SRAM单元列读取数据时，多路复用器允许第一读取位线和/或第二读取位线保持不带电。

5. 发明授权

US08127116B2 Dependency matrix with reduced area and power consumption 失效
标题翻译：具有减少面积和功耗的依赖矩阵
公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

6. 发明授权

US07561489B2 System and method of selective row energization based on write data 失效
标题翻译：基于写入数据的选择性行激励的系统和方法
公开(公告)号：US07561489B2
公开(公告)日：2009-07-14
申请号：US12125875
申请日：2008-05-22
申请人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
发明人： Michael J. Lee , Jose A. Paredes , Peter J. Klim , Sam G. Chu
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
摘要翻译：一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及响应于M行104中的每一个的均匀字数据位的M位行驱动器设备116，以禁止均匀字数据位为第一值的M行104的通电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式