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1. 发明申请

US20050055655A1 System on a chip bus with automatic pipeline stage insertion for timing closure 失效
标题翻译：系统具有自动流水线插入的片上总线，用于定时关闭
公开(公告)号：US20050055655A1
公开(公告)日：2005-03-10
申请号：US10971947
申请日：2004-10-22
申请人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sartorius , Barry Wolford
发明人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sartorius , Barry Wolford
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译：一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。相对于默认传播时间确定信号从源设备传播到目的地设备的时间。然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。使用附加逻辑，当管道级插入各种路径时，不需要更改设备。寄存器被用作插入到路径内的流水线级。

2. 发明申请

US20060031705A1 Single request data transfer regardless of size and alignment 失效
公开(公告)号：US20060031705A1
公开(公告)日：2006-02-09
申请号：US11246427
申请日：2005-10-07
申请人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sertorius , Barry Wolford
发明人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sertorius , Barry Wolford
IPC分类号： G06F5/06
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

3. 发明申请

US20060218354A1 Global modified indicator to reduce power consumption on cache miss 有权
标题翻译：全局修改指标，以降低高速缓存未命中的功耗
公开(公告)号：US20060218354A1
公开(公告)日：2006-09-28
申请号：US11088383
申请日：2005-03-23
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G06F12/0804 , G06F2212/1028 , Y02D10/13
摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.
摘要翻译：处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含已修改的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。

4. 发明申请

US20060174066A1 Fractional-word writable architected register for direct accumulation of misaligned data 审中-公开
标题翻译：用于直接累积未对齐数据的分数字可写架构寄存器
公开(公告)号：US20060174066A1
公开(公告)日：2006-08-03
申请号：US11051037
申请日：2005-02-03
申请人： Jeffrey Bridges , Victor Augsburg , James Dieffenderfer , Thomas Sartorius
发明人： Jeffrey Bridges , Victor Augsburg , James Dieffenderfer , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/30043
摘要： One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.
摘要翻译：处理器中的一个或多个架构寄存器是分数字可写的，并且来自多个未对准存储器存取操作的数据直接组装在架构化的寄存器中，而无需首先将数据组装在分数字可写，非架构化寄存器中，然后传输到建筑注册。在通用寄存器文件利用寄存器重命名或重排序缓冲器的实施例中，来自多个未对准存储器访问操作的数据直接组装在分数字可写架构寄存器中，而不需要在执行之前完全异常检查两个未对准的存储器访问操作第一个内存访问操作。

5. 发明申请

US20070174584A1 Translation lookaside buffer manipulation 有权
标题翻译：翻译后备缓冲操作
公开(公告)号：US20070174584A1
公开(公告)日：2007-07-26
申请号：US11336264
申请日：2006-01-20
申请人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/3861 , G06F12/1027
摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
摘要翻译：具有多级流水线的处理器包括TLB和TLB控制器。响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。

6. 发明申请

US20070094476A1 Updating multiple levels of translation lookaside buffers (TLBs) field 审中-公开
标题翻译：更新多个级别的翻译后备缓冲区（TLB）字段
公开(公告)号：US20070094476A1
公开(公告)日：2007-04-26
申请号：US11254898
申请日：2005-10-20
申请人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
发明人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.
摘要翻译：一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。

7. 发明申请

US20070067574A1 Method and apparatus for managing cache partitioning 有权
标题翻译：用于管理缓存分区的方法和装置
公开(公告)号：US20070067574A1
公开(公告)日：2007-03-22
申请号：US11233575
申请日：2005-09-21
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

8. 发明申请

US20070050594A1 TLB lock indicator 有权
标题翻译： TLB锁定指示灯
公开(公告)号：US20070050594A1
公开(公告)日：2007-03-01
申请号：US11210526
申请日：2005-08-23
申请人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/681
摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
摘要翻译：处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有条目。响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

9. 发明申请

US20060174090A1 Power efficient instruction prefetch mechanism 有权
公开(公告)号：US20060174090A1
公开(公告)日：2006-08-03
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

10. 发明申请

US20070180199A1 Cache locking without interference from normal allocations 有权
标题翻译：缓存锁定，不受正常分配的干扰
公开(公告)号：US20070180199A1
公开(公告)日：2007-08-02
申请号：US11343765
申请日：2006-01-31
申请人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F9/30047 , G06F9/3824
摘要： A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from main memory in the event of a cache miss; however, these instructions are not allowed to allocate entries in the cache. Only the predetermined instructions (for example, those used to establish locked cache entries) may allocate entries in the cache. When the locked entries are established, the processor exits BNCA mode, and any memory access instruction may allocate cache entries. BNCA mode may be indicated by setting a bit in a configuration register.
摘要翻译：为处理器定义块正常缓存分配（BNCA）模式。在BNCA模式中，缓存条目只能通过预定指令分配。正常存储器访问指令（例如，作为中断代码的一部分）可以执行并且将在高速缓存未命中的情况下从主存储器检索数据; 但是，这些指令不允许在缓存中分配条目。只有预定的指令（例如，用于建立锁定的高速缓存条目的指令）可以在高速缓存中分配条目。当锁定条目建立时，处理器退出BNCA模式，任何存储器访问指令都可以分配高速缓存条目。可以通过在配置寄存器中设置位来指示BNCA模式。

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