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1. 发明申请

US20070067574A1 Method and apparatus for managing cache partitioning 有权
标题翻译：用于管理缓存分区的方法和装置
公开(公告)号：US20070067574A1
公开(公告)日：2007-03-22
申请号：US11233575
申请日：2005-09-21
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

2. 发明申请

US20060200686A1 Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权
标题翻译：省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位
公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

3. 发明申请

US20060277397A1 Method and apparatus for predicting branch instructions 有权
标题翻译：用于预测分支指令的方法和装置
公开(公告)号：US20060277397A1
公开(公告)日：2006-12-07
申请号：US11144206
申请日：2005-06-02
申请人： Thomas Sartorius , Brian Stempel , Jeffrey Bridges , James Dieffenderfer , Rodney Smith
发明人： Thomas Sartorius , Brian Stempel , Jeffrey Bridges , James Dieffenderfer , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令，在分支目标缓存中丢失。因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

4. 发明申请

US20060200655A1 Forward looking branch target address caching 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：US20060200655A1
公开(公告)日：2006-09-07
申请号：US11073283
申请日：2005-03-04
申请人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F9/00
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令高速缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC获取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC的提取导致从iCache获取分支指令与从BTAC获取所需的周期相关的量。所公开的示例可以减少BTAC的写入地址或增加BTAC的获取地址，其量基本上对应于比BTAC提取所需的周期少一个量。

5. 发明申请

US20060174090A1 Power efficient instruction prefetch mechanism 有权
公开(公告)号：US20060174090A1
公开(公告)日：2006-08-03
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

6. 发明申请

US20070094475A1 Caching memory attribute indicators with cached memory data field 有权
标题翻译：使用缓存的内存数据字段缓存内存属性指示器
公开(公告)号：US20070094475A1
公开(公告)日：2007-04-26
申请号：US11254873
申请日：2005-10-20
申请人： Jeffrey Bridges , James Dieffenderfer , Thomas Sartorius , Brian Stempel , Rodney Smith
发明人： Jeffrey Bridges , James Dieffenderfer , Thomas Sartorius , Brian Stempel , Rodney Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1054 , G06F12/145 , Y02D10/13
摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.
摘要翻译：处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。存储器中的每个页面可以包括多行存储器。当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索，的数据存储在缓存行中。

7. 发明申请

US20060123326A1 Pre-decode error handling via branch correction 有权
标题翻译：通过分支校正预解码错误处理
公开(公告)号：US20060123326A1
公开(公告)日：2006-06-08
申请号：US10995858
申请日：2004-11-22
申请人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： H03M13/03
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。然后重新获取的指令被正确预解码，写入高速缓存并执行。

8. 发明申请

US20070174584A1 Translation lookaside buffer manipulation 有权
标题翻译：翻译后备缓冲操作
公开(公告)号：US20070174584A1
公开(公告)日：2007-07-26
申请号：US11336264
申请日：2006-01-20
申请人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/3861 , G06F12/1027
摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
摘要翻译：具有多级流水线的处理器包括TLB和TLB控制器。响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。

9. 发明申请

US20070094476A1 Updating multiple levels of translation lookaside buffers (TLBs) field 审中-公开
标题翻译：更新多个级别的翻译后备缓冲区（TLB）字段
公开(公告)号：US20070094476A1
公开(公告)日：2007-04-26
申请号：US11254898
申请日：2005-10-20
申请人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
发明人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.
摘要翻译：一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。

10. 发明申请

US20070050594A1 TLB lock indicator 有权
标题翻译： TLB锁定指示灯
公开(公告)号：US20070050594A1
公开(公告)日：2007-03-01
申请号：US11210526
申请日：2005-08-23
申请人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/681
摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
摘要翻译：处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有条目。响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

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