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1. 发明授权

US07865848B2 Layout optimization using parameterized cells 有权
标题翻译：使用参数化单元格进行布局优化
公开(公告)号：US07865848B2
公开(公告)日：2011-01-04
申请号：US11846017
申请日：2007-08-28
申请人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
发明人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
摘要翻译：包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。该方法可以基于与参数相关的约束来可选地调整物理设计形状。

2. 发明申请

US20090064061A1 Layout Optimization Using Parameterized Cells 有权
标题翻译：使用参数化单元格的布局优化
公开(公告)号：US20090064061A1
公开(公告)日：2009-03-05
申请号：US11846017
申请日：2007-08-28
申请人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
发明人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
摘要翻译：包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。该方法可以基于与参数相关的约束来可选地调整物理设计形状。

3. 发明授权

US07568173B2 Independent migration of hierarchical designs with methods of finding and fixing opens during migration 失效
标题翻译：在迁移过程中，分层设计的独立迁移与查找和修复方法打开
公开(公告)号：US07568173B2
公开(公告)日：2009-07-28
申请号：US11762832
申请日：2007-06-14
申请人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
发明人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
摘要翻译：公开了独立迁移分层设计的方法。一种用于迁移集成电路中的宏的方法，包括：确定宏中的基本单元与宏之间的接口策略，所述基本单元包括接口策略中涉及的接口元素; 基于接口策略相对于宏独立地移动基站; 最初缩放宏; 将迁移的基本单元交换到宏中; 并使初始缩放的宏的内容合法化。

4. 发明申请

US20080313581A1 INDEPENDENT MIGRATION OF HIERARCHICAL DESIGNS WITH METHODS OF FINDING AND FIXING OPENS DURING MIGRATION 失效
标题翻译：在移动过程中发现和固定开放方法的分层设计的独立迁移
公开(公告)号：US20080313581A1
公开(公告)日：2008-12-18
申请号：US11762832
申请日：2007-06-14
申请人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
发明人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
摘要翻译：公开了独立迁移分层设计的方法。一种用于迁移集成电路中的宏的方法，包括：确定宏中的基本单元与宏之间的接口策略，所述基本单元包括接口策略中涉及的接口元素; 基于接口策略相对于宏独立地移动基站; 最初缩放宏; 将迁移的基本单元交换到宏中; 并使初始缩放的宏的内容合法化。

5. 发明授权

US07735042B2 Context aware sub-circuit layout modification 失效
标题翻译：上下文感知子电路布局修改
公开(公告)号：US07735042B2
公开(公告)日：2010-06-08
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

6. 发明申请

US20090037850A1 POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS 审中-公开
标题翻译：用于VLSI LAYOUTS的多边形设计规则校正方法
公开(公告)号：US20090037850A1
公开(公告)日：2009-02-05
申请号：US11831990
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last “next LP problem” is solved using constraints and objectives representing sums or differences of no more than two optimization variables.
摘要翻译：一种多边形区域设计规则校正方法，用于电子设计自动化工具，用于使用一维（1-D）优化来管理集成电路（IC）设计布局，并分析IC设计布局数据以识别违反多边形，划分在优化方向上将多边形侵入矩形，为每个违规多边形制定面积约束以制定全局线性规划（LP）问题，其包括每个违反多边形的每个约束，并解决全局LP问题以获得实值解。为每个区域约束创建下一个LP问题，并解决。重复创建下一个LP并解决下一个LP问题和解决问题，直到最后的“下一个LP问题”使用表示不超过两个优化变量的和或差的约束和目标来解决。

7. 发明申请

US20090037851A1 CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
标题翻译：背景知识子电路布局修改
公开(公告)号：US20090037851A1
公开(公告)日：2009-02-05
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

8. 发明授权

US07490308B2 Method for implementing overlay-based modification of VLSI design layout 失效
标题翻译：实现基于覆盖的VLSI设计布局修改方法
公开(公告)号：US07490308B2
公开(公告)日：2009-02-10
申请号：US11278162
申请日：2006-03-31
申请人： Christopher J. Gonzalez , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen I. Runyon , Xiaoyun K. Wu
发明人： Christopher J. Gonzalez , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen I. Runyon , Xiaoyun K. Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/08
摘要： A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.
摘要翻译：修改用于性能优化的VLSI布局的方法包括为要修改的多个原始设备形状定义修改的基本规则集，并将多个原始设备形状平坦化为主单元。基于经修改的基础规则集，对平坦化的设备形状执行布局优化操作，以便创建多个修改的设备形状。然后从修改的设备形状和原始设备形状之间的差异创建覆盖单元。

9. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

10. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

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