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1. 发明授权

US07503021B2 Integrated circuit diagnosing method, system, and program product 失效
标题翻译：集成电路诊断方法，系统和程序产品
公开(公告)号：US07503021B2
公开(公告)日：2009-03-10
申请号：US11160266
申请日：2005-06-16
申请人： Matt Boucher , John M. Cohn , Richard Dauphin , Mark Masters , Judith H. McCullen , Sarah C. Braasch , Michael H. Sitko
发明人： Matt Boucher , John M. Cohn , Richard Dauphin , Mark Masters , Judith H. McCullen , Sarah C. Braasch , Michael H. Sitko
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/3025 , G01R31/303
摘要： The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.
摘要翻译：本发明提供了用于诊断集成电路的方法，系统和程序产品。特别地，本发明为集成电路的每个相关电路层捕获一个或多个图像。基于图像，生成组件网表。此外，通过将分层组合规则应用于组件网表生成逻辑网表。组件网表和/或逻辑网表可以与参考网表进行比较以诊断集成电路。本发明还可以根据从网表确定的端口，功率和/或组件引脚连接信息，组件网络表或逻辑网表，其中组件被布置。此外，可以以选择性地显示布线连接以辅助用户智能地布置电路部件的方式来显示原理图。

2. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

3. 发明申请

US20080127004A1 METHOD FOR COMPUTING THE CRITICAL AREA OF COMPOUND FAULT MECHANISMS 失效
标题翻译：计算化合物故障机理关键领域的方法
公开(公告)号：US20080127004A1
公开(公告)日：2008-05-29
申请号：US11461805
申请日：2006-08-02
申请人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
发明人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method of calculating critical area based on both independent and dependent compound fault mechanisms. This critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.
摘要翻译：公开了一种基于独立和依赖复合故障机制来计算临界面积的方法。该关键区域通过为复合故障机制中的每个简单故障机制产生由多边形区域组成的地图来计算，其中第三维z轴上的值表示在点x处的每个单个故障机制的临界缺陷尺寸，y。覆盖这些贴图，并且将每个贴图的每个区域的平面（即，顶面）投影到x，y平面上，以便识别相交的子区域。基于对预定布尔表达式的答案来识别每个子区域内的主要故障机制，并且累积所有子区域的临界区域以获得复合故障机制的总临界面积。

4. 发明授权

US07752580B2 Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique 有权
标题翻译：基于使用开放确定性测序技术选择的样本窗口来分析集成电路的方法和系统
公开(公告)号：US07752580B2
公开(公告)日：2010-07-06
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

5. 发明授权

US07634745B2 Method for computing the critical area of compound fault mechanisms 失效
标题翻译：计算复合故障机制关键区域的方法
公开(公告)号：US07634745B2
公开(公告)日：2009-12-15
申请号：US11461805
申请日：2006-08-02
申请人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
发明人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In embodiments of a method critical area is calculated based on both independent and dependent compound fault mechanisms. Specifically, critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.
摘要翻译：在方法的实施例中，基于独立和依赖复合故障机制来计算关键区域。具体地说，关键区域是通过为复合故障机构中的每个简单故障机制产生由多边形区域组成的地图来计算的，其中第三维z轴上的值表示在一个点处的每个单个故障机构的临界缺陷尺寸 x，y。覆盖这些贴图，并且将每个贴图的每个区域的平面（即顶面）投影到x，y平面上，以便识别相交的子区域。基于对预定布尔表达式的答案来识别每个子区域内的主要故障机制，并且累积所有子区域的临界区域以获得复合故障机制的总临界面积。

6. 发明申请

US20090031263A1 METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE 有权
标题翻译：基于使用开放式确定性测序技术选择的样本窗口分析集成电路的方法和系统
公开(公告)号：US20090031263A1
公开(公告)日：2009-01-29
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

7. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

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