专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09768055B2 Isolation regions for SOI devices 有权
公开(公告)号：US09768055B2
公开(公告)日：2017-09-19
申请号：US13590836
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

2. 发明授权

US08703550B2 Dual shallow trench isolation liner for preventing electrical shorts 有权
标题翻译：双浅沟槽隔离衬垫，用于防止电气短路
公开(公告)号：US08703550B2
公开(公告)日：2014-04-22
申请号：US13525642
申请日：2012-06-18
申请人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
摘要翻译：形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。随后形成栅极结构和源极/漏极结构。氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

3. 发明申请

US20130334651A1 DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS 有权
标题翻译：用于防止电气短路的双层防爆隔离衬套
公开(公告)号：US20130334651A1
公开(公告)日：2013-12-19
申请号：US13525642
申请日：2012-06-18
申请人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
摘要翻译：形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。随后形成栅极结构和源极/漏极结构。氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

4. 发明授权

US08828851B2 Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering 有权
标题翻译：用于形成用于PFET阈值电压工程的FDSOI器件的硅锗通道的方法
公开(公告)号：US08828851B2
公开(公告)日：2014-09-09
申请号：US13487583
申请日：2012-06-04
申请人： Nicolas Loubet , Prasanna Khare , Qing Liu
发明人： Nicolas Loubet , Prasanna Khare , Qing Liu
IPC分类号： H01L21/336 , H01L21/20 , H01L29/78
CPC分类号： H01L21/84 , H01L27/1207 , H01L29/66477 , H01L29/66628 , H01L29/7848
摘要： An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.
摘要翻译： SOI衬底具有与第二区域隔离的第一区域。 SiGe层沉积在第二区域中的SOI衬底的顶部上。对衬底进行热氧化处理，其在GeGe层中驱动Ge，以在第二区域和上覆氧化物层中形成SiGeOI结构。如果SOI衬底在第一区域中暴露，则热氧化工艺进一步产生覆盖第一区域的氧化物层。去除氧化物层以暴露第一区域中的Si沟道层和第二区域中的SiGe沟道层。在每个Si沟道层和SiGe沟道层上形成晶体管栅极叠层。上升的源极和漏极区域由Si沟道层和与晶体管栅极叠层相邻的SiGe沟道层形成。

5. 发明授权

US08796147B2 Layer formation with reduced channel loss 有权
标题翻译：层形成减少了通道损耗
公开(公告)号：US08796147B2
公开(公告)日：2014-08-05
申请号：US12971054
申请日：2010-12-17
申请人： Nicolas Loubet , Qing Liu , Prasanna Khare
发明人： Nicolas Loubet , Qing Liu , Prasanna Khare
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L29/1033 , H01L29/04 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/78
摘要： Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
摘要翻译：可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。可以在栅极区域和半导体器件区域上形成第一绝缘层。可以在第一绝缘层上形成第二绝缘层。可以在第二绝缘层上形成第三绝缘层。可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

6. 发明申请

US20130193514A1 METHOD TO ENABLE THE FORMATION OF SILICON GERMANIUM CHANNEL OF FDSOI DEVICES FOR PFET THRESHOLD VOLTAGE ENGINEERING 有权
标题翻译：用于形成用于PFET阈值电压工程的FDSOI器件的硅锗通道的方法
公开(公告)号：US20130193514A1
公开(公告)日：2013-08-01
申请号：US13487583
申请日：2012-06-04
申请人： Nicolas Loubet , Prasanna Khare , Qing Liu
发明人： Nicolas Loubet , Prasanna Khare , Qing Liu
IPC分类号： H01L21/336 , H01L21/20 , H01L29/78
CPC分类号： H01L21/84 , H01L27/1207 , H01L29/66477 , H01L29/66628 , H01L29/7848
摘要： An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.
摘要翻译： SOI衬底具有与第二区域隔离的第一区域。 SiGe层沉积在第二区域中的SOI衬底的顶部上。对衬底进行热氧化处理，其在GeGe层中驱动Ge，以在第二区域和上覆氧化物层中形成SiGeOI结构。如果SOI衬底在第一区域中暴露，则热氧化工艺进一步产生覆盖第一区域的氧化物层。去除氧化物层以暴露第一区域中的Si沟道层和第二区域中的SiGe沟道层。在每个Si沟道层和SiGe沟道层上形成晶体管栅极叠层。上升的源极和漏极区域由Si沟道层和与晶体管栅极叠层相邻的SiGe沟道层形成。

7. 发明授权

US09093556B2 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods 有权
标题翻译：多翅鳍FINFET器件，其包括在最外鳍的外表面上的外延生长阻挡层和相关方法
公开(公告)号：US09093556B2
公开(公告)日：2015-07-28
申请号：US13590756
申请日：2012-08-21
申请人： Qing Liu , Prasanna Khare , Nicolas Loubet
发明人： Qing Liu , Prasanna Khare , Nicolas Loubet
IPC分类号： H01L29/76 , H01L21/8238 , H01L21/84 , H01L29/66 , H01L29/78 , H01L29/08 , H01L21/265 , H01L29/417
CPC分类号： H01L27/0886 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/823418 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L29/0847 , H01L29/41783 , H01L29/41791 , H01L29/66795 , H01L29/66803 , H01L29/785
摘要： A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
摘要翻译：多鳍FINFET器件可以包括衬底和从衬底向上延伸并沿着衬底间隔开的多个半导体鳍片。每个半导体鳍片可以具有相对的第一和第二端以及它们之间的中间部分，并且多个半导体鳍片的最外面的鳍片可以在其外表面上包括外延生长阻挡层。 FINFET还可以包括覆盖半导体鳍片的中间部分的至少一个栅极，在与其第一端相邻的半导体鳍片之间的多个凸起的外延半导体源极区域和在相邻的半导体鳍片之间的多个凸起的外延半导体漏极区域其第二端。

8. 发明申请

US20140054698A1 ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS 有权
标题翻译：电子设备，包括具有底部氮化物衬里和上氧化物衬里的浅层分离（STI）区域及相关方法
公开(公告)号：US20140054698A1
公开(公告)日：2014-02-27
申请号：US13590703
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/762 , H01L21/76202 , H01L21/76224 , H01L21/76264
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋氧化物（BOX）层，覆盖BOX层的至少一个半导体器件，以及衬底中的至少一个STI区域，并与该至少一个半导体器件相邻。所述至少一个STI区域限定与所述衬底的侧壁表面，并且可以包括衬在所述侧壁表面的底部部分的氮化物层，在所述底部部分的上方衬着所述侧壁表面的顶部的氧化物层以及所述侧壁表面内的绝缘材料氮化物和氧化物层。

9. 发明申请

US20120142121A1 HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION 有权
标题翻译：在一个单一的室中的氢氯酸盐和低温外延，用于提高源水排放
公开(公告)号：US20120142121A1
公开(公告)日：2012-06-07
申请号：US12960736
申请日：2010-12-06
申请人： Prasanna Khare , Nicolas Loubet , Qing Liu
发明人： Prasanna Khare , Nicolas Loubet , Qing Liu
IPC分类号： H01L21/306
CPC分类号： H01L21/02661 , H01L21/02639 , H01L29/66628 , H01L29/66636
摘要： A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
摘要翻译：使用其中半导体结构被接收在适于支持蚀刻工艺和外延生长工艺两者的处理室中的工艺来形成凸起的源极 - 漏极结构。该半导体结构包括源极区和漏极区，其中源区和漏区各自包括受损的表面层。控制处理室以设定所需的气氛并设定所需的温度。在所需的气氛和温度下，处理室的蚀刻过程用于从源极和漏极区域去除损坏的表面层并暴露界面。在不释放期望的气氛的同时保持期望的温度，处理室的外延生长过程用于从暴露的界面表面生长在源极和漏极区之上的凸起区域。

10. 发明授权

US09012999B2 Semiconductor device with an inclined source/drain and associated methods 有权
标题翻译：具有倾斜源极/漏极和相关方法的半导体器件
公开(公告)号：US09012999B2
公开(公告)日：2015-04-21
申请号：US13590548
申请日：2012-08-21
申请人： Qing Liu , Prasanna Khare , Nicolas Loubet
发明人： Qing Liu , Prasanna Khare , Nicolas Loubet
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/70 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/76816 , H01L21/823425 , H01L21/823864 , H01L29/41766 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.
摘要翻译：半导体器件包括其中具有沟道区域的半导体衬底，沟道区域上方的栅极结构以及栅极结构的相对侧上的源极和漏极区域。每个源极和漏极区域上都有一个相应的触点。源极和漏极区域中的至少一个具有与相应触点的倾斜上接触表面。倾斜的上接触表面具有比相应的平坦接触表面至少大50％的面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式