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1. 发明授权

US07325210B2 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权
标题翻译：混合线性线模型方法来调整具有RC互连的电路的晶体管宽度
公开(公告)号：US07325210B2
公开(公告)日：2008-01-29
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译：描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。目前的混合方法实现了计算速度的显着提高。面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配。这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

2. 发明授权

US07743355B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07743355B2
公开(公告)日：2010-06-22
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

3. 发明授权

US07093208B2 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices 失效
标题翻译：用于在连续设计空间中调整合成随机逻辑电路宏的数字设计的方法，并可选择插入多个阈值电压器件
公开(公告)号：US07093208B2
公开(公告)日：2006-08-15
申请号：US10842589
申请日：2004-05-10
申请人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
发明人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
摘要翻译：可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。调整受限于将设计映射回固定单元格时最小化“合并错误”。此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

4. 发明授权

US07003747B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07003747B2
公开(公告)日：2006-02-21
申请号：US10435824
申请日：2003-05-12
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

5. 发明授权

US07010763B2 Method of optimizing and analyzing selected portions of a digital integrated circuit 有权
标题翻译：优化和分析数字集成电路的选定部分的方法
公开(公告)号：US07010763B2
公开(公告)日：2006-03-07
申请号：US10436213
申请日：2003-05-12
申请人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
发明人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.
摘要翻译：公开了一种在数字集成电路或系统的设计中实现定时闭合的方法，通过选择要优化的电路或系统的部分以及在优化期间分析这种优化的影响的电路或系统的部分处理。优化部分将包括其设计参数将被改变的门，第一分析部分包括要重新计算其延迟和边缘电压的门，并且第二分析部分包括在优化期间重新计算其AT和RAT的门。在这些部分之间的选定边界施加约束，以防止定时信息的不期望的传播，并确保优化期间使用的定时值的有效性。通过这种选择，将降低对基础优化方法造成的问题的大小，从而允许更大的电路或系统被优化，并允许更快地执行优化。

6. 发明授权

US07627836B2 OPC trimming for performance 失效
标题翻译： OPC修剪性能
公开(公告)号：US07627836B2
公开(公告)日：2009-12-01
申请号：US11164044
申请日：2005-11-08
申请人： James A. Culp , Lars W. Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen L. Runyon , Patrick M. Williams
发明人： James A. Culp , Lars W. Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen L. Runyon , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
摘要翻译：基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。标记形状识别构成关键定时路径中的装置的电路的预定子组。根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。使用OPC技术为所选的关键设备制作掩码。

7. 发明授权

US08239804B2 Method for calculating capacitance gradients in VLSI layouts using a shape processing engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US08239804B2
公开(公告)日：2012-08-07
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

8. 发明授权

US07971171B2 Method and system for electromigration analysis on signal wiring 有权
标题翻译：信号线路电迁移分析方法与系统
公开(公告)号：US07971171B2
公开(公告)日：2011-06-28
申请号：US12123769
申请日：2008-05-20
申请人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
发明人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.
摘要翻译：本发明涉及电迁移分析方法和用于分析处于电迁移风险的数字集成电路设计中的一个或多个网络的系统。该方法包括以下步骤：在驱动器单元和至少一个称重传感器之间提供至少一个互连; 应用相同的提取网表数据进行噪声和/或定时分析和电迁移分析; 通过所述至少一个互连通过从所述驱动器单元传输到所述一个或多个称重传感器的一串梯形电压脉冲对所述驱动器单元进行建模; 从所述一个或多个网络的噪声和/或定时分析中提取至少一个驱动器电压信号和/或定时信息的转换速率; 以及将所述至少一个互连中的局部测量的电流密度与所述至少一个互连的有效局部最大电流密度极限进行比较。

9. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

10. 发明申请

US20090013290A1 Method and System for Electromigration Analysis on Signal Wiring 有权
标题翻译：信号接线电迁移分析方法与系统
公开(公告)号：US20090013290A1
公开(公告)日：2009-01-08
申请号：US12123769
申请日：2008-05-20
申请人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
发明人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (UD) and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density (if,rms,R32) in the at least one interconnect to an effective local maximum current density limit (irms,max) of the at least one interconnect.
摘要翻译：本发明涉及电迁移分析方法和用于分析处于电迁移风险的数字集成电路设计中的一个或多个网络的系统。该方法包括以下步骤：在驱动器单元和至少一个称重传感器之间提供至少一个互连; 应用相同的提取网表数据进行噪声和/或定时分析和电迁移分析; 通过所述至少一个互连通过从所述驱动器单元传输到所述一个或多个称重传感器的一串梯形电压脉冲对所述驱动器单元进行建模; 从所述一个或多个网络的噪声和/或定时分析中提取至少一个驱动器电压信号（UD）的转换速率和/或定时信息; 以及将所述至少一个互连中的局部测量的电流密度（if，rms，R32）与所述至少一个互连的有效局部最大电流密度极限（irms，max）进行比较。

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