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1. 发明申请

US20100262940A1 Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in VLSI Layouts in the Presence of Catastrophic Optical Proximity Correction 有权
标题翻译：在具有不规则偏移的电线中的电阻的精确近似以及在存在灾难性光学邻近校正的VLSI布局中确定互连电容
公开(公告)号：US20100262940A1
公开(公告)日：2010-10-14
申请号：US12423387
申请日：2009-04-14
申请人： Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
发明人： Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.
摘要翻译：宽度偏差计算器（WBC）通过有效地将电气值平均为目标线材形状的任一侧来计算电气值，从而将值近似于设计验证，而不会对性能或存储器消耗产生显着影响。

2. 发明授权

US08495540B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 失效
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08495540B2
公开(公告)日：2013-07-23
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

3. 发明授权

US08245169B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 有权
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08245169B2
公开(公告)日：2012-08-14
申请号：US12648456
申请日：2009-12-29
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

4. 发明申请

US20120185815A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20120185815A1
公开(公告)日：2012-07-19
申请号：US13427516
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

5. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

6. 发明授权

US07844435B2 Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：具有片上信号完整性和使用频率相关RLC提取和建模技术的噪声验证的集成电路芯片
公开(公告)号：US07844435B2
公开(公告)日：2010-11-30
申请号：US11942270
申请日：2007-11-19
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音补音R12的频率相关RL电路的技术。

7. 发明授权

US07475372B2 Methods for computing Miller-factor using coupled peak noise 失效
标题翻译：使用耦合峰值噪声计算米勒因子的方法
公开(公告)号：US07475372B2
公开(公告)日：2009-01-06
申请号：US11160701
申请日：2005-07-06
申请人： Chandramouli V. Kashyap , Gregory Michael Schaeffer , David J. Widiger
发明人： Chandramouli V. Kashyap , Gregory Michael Schaeffer , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for computing a Miller-factor compensated for peak noise provided. The method includes mapping at least two delays as function of at least two Miller-factors; determining an equation of the function; computing a peak noise; computing a peak delay resulting from the peak noise; and computing the compensated Miller-factor based on the equation and the peak delay. The function can be either a linear function or a non-linear function.
摘要翻译：一种用于计算提供的峰值噪声补偿的米勒因子的方法。该方法包括将至少两个延迟映射为至少两个米勒因子的函数; 确定函数的方程; 计算峰值噪声; 计算由峰值噪声引起的峰值延迟; 并根据方程和峰值延迟计算补偿的米勒因子。该函数可以是线性函数或非线性函数。

8. 发明授权

US08645899B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08645899B2
公开(公告)日：2014-02-04
申请号：US12415266
申请日：2009-03-31
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

9. 发明申请

US20120204140A1 Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills 失效
标题翻译：在金属填充物的情况下生成接线图形的电容查找表
公开(公告)号：US20120204140A1
公开(公告)日：2012-08-09
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

10. 发明授权

US07346867B2 Method for estimating propagation noise based on effective capacitance in an integrated circuit chip 失效
标题翻译：基于集成电路芯片中的有效电容估计传播噪声的方法
公开(公告)号：US07346867B2
公开(公告)日：2008-03-18
申请号：US11048422
申请日：2005-02-01
申请人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
发明人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.
摘要翻译：用于估计在驱动器电路的输入处由非零噪声毛刺引起的传播噪声的系统和方法。这种传播噪声是输入噪声毛刺和驱动器输出有效电容性负载两者的函数，这通常是由于深亚微米互连中的电阻屏蔽而导致的总布线电容的一部分。本文提供的噪声驱动的有效电容解决方案还估计在驱动门的输入处由非零噪声毛刺引起的传播噪声。在噪声驱动的有效电容过程中使用描述输出噪声特性和输入噪声特性与输出负载电容之间的关系的门传播噪声规则来确定驱动门的线性戴维宁模型。然后使用线性化的戴维南驱动器模型来分析传播噪声和通常在全局信号网中看到的组合耦合和传播噪声。

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