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1. 发明授权

US5540379A Soldering process 失效
标题翻译：焊接工艺
公开(公告)号：US5540379A
公开(公告)日：1996-07-30
申请号：US236611
申请日：1994-05-02
申请人： Vahid Kazem-Goudarzi , Henry F. Liebman , Kingshuk Banerji , William B. Mullen, III , Edwin L. Bradley, III
发明人： Vahid Kazem-Goudarzi , Henry F. Liebman , Kingshuk Banerji , William B. Mullen, III , Edwin L. Bradley, III
IPC分类号： B23K35/02 , B23K35/26 , H05K3/34
CPC分类号： B23K35/0244 , B23K35/26 , H05K3/3484 , B23K35/025 , H05K2201/0272 , H05K2203/043 , H05K3/3463
摘要： A soldering process using two different types of solder alloys is disclosed. The first solder alloy (115) undergoes a solid-to-liquid transition at a first temperature. The second solder alloy (120) undergoes this solid-to-liquid transition at a second temperature, the second temperature being greater than the first temperature. The soldering composition is deposited (20) on a substrate (100) having solderable portions (105) and is heated to a temperature that is above the first temperature but below the second temperature (32). During this time, the first solder alloy liquifies, while the second solder alloy remains solid. The soldering composition is subsequently cooled (40) to solidify the first solder material. A part or electronic component is added (80) to the solidified solder material and the solder materials is again heated above the second temperature (30) in order to reflow the solder and form a metallurgical bond between the substrate and the electronic component.
摘要翻译：公开了使用两种不同类型的焊料合金的焊接工艺。第一焊料合金（115）在第一温度下经历固 - 液转变。第二焊料合金（120）在第二温度下经历该固 - 液转变，第二温度大于第一温度。将焊接组合物沉积在具有可焊接部分（105）的基底（100）上，并被加热到高于第一温度但低于第二温度（32）的温度。在此期间，第一焊料合金液化，而第二焊料合金保持固体。焊接组合物随后被冷却（40）以固化第一焊料材料。向固化的焊料材料添加部件或电子部件（80），并且焊料材料再次被加热到高于第二温度（30）以便回流焊料并在基板和电子部件之间形成冶金结合。

2. 发明授权

US5427865A Multiple alloy solder preform 失效
标题翻译：多合金焊料预制件
公开(公告)号：US5427865A
公开(公告)日：1995-06-27
申请号：US236614
申请日：1994-05-02
申请人： William B. Mullen, III , Kingshuk Banerji , Edwin L. Bradley, III , Vahid Kazem-Goudarzi
发明人： William B. Mullen, III , Kingshuk Banerji , Edwin L. Bradley, III , Vahid Kazem-Goudarzi
IPC分类号： B23K35/02 , B23K35/14 , B23K35/26 , H05K3/34 , B22F7/02
CPC分类号： B23K35/0244 , B23K35/262 , H05K3/3484 , H05K2201/0272 , H05K2203/0338 , H05K2203/043 , H05K3/3452 , H05K3/3463 , Y10T428/12014 , Y10T428/12028 , Y10T428/12063 , Y10T428/12097 , Y10T428/12104 , Y10T428/1216
摘要： A solder preform (250) has solder particles of one alloy (210) arranged within a matrix of a second solder alloy (200). This arrangement forms a structure having the desired predetermined shape of the solder preform. The solder particles comprise one or more of the following elements: tin, lead, bismuth, indium, copper, antimony, cadmium, arsenic, aluminum, gallium, gold, silver. The particles have a predetermined melting temperature. The second solder alloy is compositionally distinct from the solder particles, and has a melting temperature that is lower than the melting temperature of the solder particles. The solder particles may comprise about 88% by weight of the solder preform, and the second solder alloy comprises about 12% by weight of the preform.
摘要翻译：焊料预制件（250）具有布置在第二焊料合金（200）的基体内的一个合金（210）的焊料颗粒。这种布置形成了具有所需预定形状的焊料预制件的结构。焊料颗粒包括以下元素中的一种或多种：锡，铅，铋，铟，铜，锑，镉，砷，铝，镓，金，银。颗粒具有预定的熔融温度。第二焊料合金在组成上不同于焊料颗粒，并且具有低于焊料颗粒的熔化温度的熔化温度。焊料颗粒可以包含约88重量％的焊料预制件，第二焊料合金占预制件的约12重量％。

3. 发明授权

US5623127A Single alloy solder clad substrate 失效
标题翻译：单合金焊包覆基板
公开(公告)号：US5623127A
公开(公告)日：1997-04-22
申请号：US348427
申请日：1994-12-02
申请人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
发明人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
IPC分类号： B23K35/14 , B23K35/26 , H05K3/24 , H05K3/34 , H05K1/02
CPC分类号： B23K35/262 , H05K3/3484 , H05K2203/043 , H05K3/3463
摘要： A solder clad printed circuit board (100) consists of an electrically insulating substrate that has copper circuit traces (105), portions of which are solderable. A substantially planar layer (120) of a soldering composition is fused to the solderable traces, to form a solder pad that is not domed. The layer is composed of a mass of off-eutectic solder particles (115) that are fused together to form an agglomeration (120) having a porous structure. The solder particles are fused together by heating the off-eutectic solder to a temperature that is between the solidus temperature and the liquidus temperature of the solder. The solder is then cooled below the solidus temperature to solidify it.
摘要翻译：焊料包覆印刷电路板（100）由具有铜电路迹线（105）的电绝缘基板组成，其一部分是可焊接的。焊接组合物的基本平坦的层（120）被熔合到可焊接迹线，以形成不是圆顶的焊盘。该层由大量的非共熔焊料颗粒（115）组成，它们被熔合在一起以形成具有多孔结构的附聚物（120）。通过将非共晶焊料加热到固相线温度和焊料的液相线温度之间的温度将焊料颗粒熔合在一起。然后将焊料冷却至固相线温度以使其固化。

4. 发明授权

US5311059A Backplane grounding for flip-chip integrated circuit 失效
标题翻译：背板接地用于倒装芯片集成电路
公开(公告)号：US5311059A
公开(公告)日：1994-05-10
申请号：US825367
申请日：1992-01-24
申请人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
发明人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L23/14 , H01L23/24 , H01L23/58
CPC分类号： H01L23/585 , H01L21/56 , H01L21/563 , H01L23/145 , H01L23/24 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2924/01014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15151 , H01L2924/15311
摘要： A semiconductor device package comprises a substrate (20) having a metallization pattern (22) on at least one surface, and a semiconductor device (10) having an active surface (12) and a grounded surface (14) on opposed sides. The semiconductor device is electrically attached to the substrate metallization pattern with the active surface (12) facing the substrate. A polymeric underfill material (30) substantially fills the space between the semiconductor device and the substrate. An electrically conductive material (35) covers the exposed grounded surface (14) of the semiconductor device and at least a portion of the metallization pattern (22), providing electrical connection between the grounded surface of the semiconductor and the metallization pattern (22) on the substrate.
摘要翻译：半导体器件封装包括在至少一个表面上具有金属化图案（22）的衬底（20）和在相对侧上具有有源表面（12）和接地表面（14）的半导体器件（10）。半导体器件电连接到衬底金属化图案，其中有源表面（12）面向衬底。聚合物底部填充材料（30）基本上填充半导体器件和衬底之间的空间。导电材料（35）覆盖半导体器件的暴露的接地表面（14）和金属化图案（22）的至少一部分，在半导体的接地表面和金属化图案（22）之间提供电连接，底物。

5. 发明授权

US5446625A Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface 失效
标题翻译：芯片载体具有在一个表面上镀金并且在另一个表面上没有金的铜图案
公开(公告)号：US5446625A
公开(公告)日：1995-08-29
申请号：US365988
申请日：1994-12-28
申请人： Glenn F. Urbish , William B. Mullen, III , Kingshuk Banerji
发明人： Glenn F. Urbish , William B. Mullen, III , Kingshuk Banerji
IPC分类号： H01L23/31 , H01L23/498 , H05K7/02 , H01L23/28 , H05K1/18
CPC分类号： H01L23/498 , H01L23/3121 , H01L2224/05644 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L24/45 , H01L24/48 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311
摘要： A chip carrier (20) includes a substrate (11) having a first copper pattern (12) deposited on a first surface (13), and a second copper pattern (14) deposited on a second surface (16). The second copper pattern (14) is plated with a metallic material to form wire bondable areas (18) on the second copper pattern (14), however, the first copper pattern (12) is substantially devoid of the metallic material. A device (21) is wire bonded to the wire bondable areas (18) of the second copper pattern (14), and a protective covering (23) covers the wire bondable areas (18).
摘要翻译：芯片载体（20）包括具有沉积在第一表面（13）上的第一铜图案（12）的基底（11）和沉积在第二表面（16）上的第二铜图案。第二铜图案（14）镀有金属材料，以在第二铜图案（14）上形成可焊接区域（18），然而，第一铜图案（12）基本上不含金属材料。将装置（21）引线接合到第二铜图案（14）的可焊接区域（18），并且保护覆盖物（23）覆盖可焊接区域（18）。

6. 发明授权

US5293067A Integrated circuit chip carrier 失效
标题翻译：集成电路芯片载体
公开(公告)号：US5293067A
公开(公告)日：1994-03-08
申请号：US898231
申请日：1992-06-12
申请人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
发明人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
IPC分类号： H01L23/12 , H01L21/56 , H01L23/32 , H01L23/498 , H01L23/02
CPC分类号： H01L23/49827 , H01L21/563 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01004 , H01L2924/15311
摘要： An integrated circuit chip carrier assembly, comprising a semiconductor device (10) having interconnection pads (14) disposed on an active surface (12) of the device. The device (10) is attached by means of electrically conducting bumps (26) to a circuitry pattern (18) on a first side of a circuit carrying substrate (16). The substrate is typically an aramid reinforced organic resin, such as epoxy. The circuitry (18, 20) is electrically connected by conductive through-holes (22) to an array of solder pads on a second side of the substrate. Some or all of the through-holes (22) are covered by the device. The overall length and width of the circuit carrying substrate (16) are each a maximum of about 0.15 inches greater than the equivalent dimensions of the device (10), creating a carrier that is only slightly larger than the semiconductor device itself.
摘要翻译：一种集成电路芯片载体组件，包括具有布置在所述装置的有效表面（12）上的互连焊盘（14）的半导体器件（10）。装置（10）通过导电凸块（26）连接到电路承载衬底（16）的第一侧上的电路图案（18）。基底通常是芳族聚酰胺增强的有机树脂，例如环氧树脂。电路（18,20）通过导电通孔（22）电连接到衬底的第二侧上的焊盘阵列。一些或全部通孔（22）被装置覆盖。电路承载基板（16）的总长度和宽度各自最大大约为装置（10）的等效尺寸约0.15英寸，从而形成仅略大于半导体装置本身的载体。

7. 发明授权

US5177134A Tacking agent 失效
标题翻译：取款代理
公开(公告)号：US5177134A
公开(公告)日：1993-01-05
申请号：US622027
申请日：1990-12-03
申请人： William B. Mullen, III , Anthony B. Suppelsa , Robert W. Pennisi
发明人： William B. Mullen, III , Anthony B. Suppelsa , Robert W. Pennisi
IPC分类号： B23K35/363 , B23K35/14 , B23K35/36 , C08K5/00 , C08L69/00 , C09J109/00 , C09J133/00 , C09J133/04 , C09J167/00 , C09J167/02 , H05K3/30 , H05K3/34
CPC分类号： B23K35/3612 , B23K35/3618 , H05K3/305 , H05K3/3489 , H05K2203/0485 , Y02P70/613
摘要： A tacking agent is provided for use in temporarily adhering electronic components and providing fluxing properties for soldering electronic assemblies. The tacking agent comprises a fluxing agent and a tackifier. The fluxing agent is composed of one or more carboxylic acids having the formula ##STR1## where R is an alkyl group containing from 1 to 6 carbon atoms, R' is selected from the group consisting of hydrogen and hydroxyl, and R" is selected from the group consisting of hydrogen, hydroxyl and carboxyl. The tackifier comprises one or more alcohols, aromatic hydrocarbon solvents, aliphatic hydrocarbon solvents, or polymers. The tacking agent is deposited onto a printed circuit board or other substrate, the electronic components are placed into the deposited tacking agent and soldered. During solder reflow the fluxing agent provides fluxing action for the soldering process, and the tackifier volatilizes, leaving little or no residue on the printed circuit board.
摘要翻译：提供了一种用于临时粘附电子部件并提供焊接电子组件的助焊剂性质的粘合剂。粘合剂包括助熔剂和增粘剂。助熔剂由一种或多种具有式“IMAGE”的羧酸组成，其中R是含有1至6个碳原子的烷基，R'选自氢和羟基，R“被选择由氢，羟基和羧基组成的组。增粘剂包括一种或多种醇，芳烃溶剂，脂族烃溶剂或聚合物。将定影剂沉积在印刷电路板或其它基底上，将电子部件放入沉积的粘合剂中并进行焊接。在焊锡回流期间，助熔剂为焊接工艺提供助熔作用，增粘剂挥发，在印刷电路板上留下很少或没有残留物。

8. 发明授权

US5338391A Method of making a substrate having selectively releasing conductive runners 失效
标题翻译：制造具有选择性释放导电流道的基板的方法
公开(公告)号：US5338391A
公开(公告)日：1994-08-16
申请号：US134447
申请日：1993-10-12
申请人： Anthony B. Suppelsa , William B. Mullen, III , Glenn F. Urbish
发明人： Anthony B. Suppelsa , William B. Mullen, III , Glenn F. Urbish
IPC分类号： C23C14/02 , H01L21/48 , H01L21/60 , H05K3/38 , H05K3/40 , B44C1/22 , C23F1/00
CPC分类号： H01L24/81 , C23C14/025 , H01L21/4846 , H05K3/4092 , H01L2224/16 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H05K3/388
摘要： A selectively releasing runner and substrate assembly (10) comprises a plurality of conductive runners (16) adhered to a substrate (12). A portion (18) of at least some of the conductive runners have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to thermal stress. The selectively releasing runner and substrate assembly is made by selectively depositing an adhesion layer (14) of a first metal to portions of the surface of the substrate where maximum adhesion is desired. The other portions of the substrate are not covered with the first metal. The first metal layer and the uncovered portions of the substrate surface are covered with a second metal layer (16). The adhesion of the second metal layer to the substrate is less than the adhesion of the second metal layer to the first metal layer, and less than the adhesion of the first metal layer tot he substrate. The second metal layer may be copper. Additionally, an electronic component (22), such as an integrated circuit, may be attached to the selectively releasing metal portion.
摘要翻译：选择性释放流道和基底组件（10）包括粘附到基底（12）的多个导电流道（16）。至少一些导电流道的一部分（18）对基底具有较低的粘合力，用于当受到热应力时从基底中选择性地释放导电流道。通过选择性地将第一金属的粘合层（14）沉积到需要最大粘合力的基底表面的部分上来制备选择性释放流道和基底组件。基板的其它部分不被第一金属覆盖。衬底表面的第一金属层和未覆盖部分被第二金属层（16）覆盖。第二金属层对基板的粘合力小于第二金属层与第一金属层的密合性，小于第一金属层与基板的粘合性。第二金属层可以是铜。此外，诸如集成电路的电子部件（22）可以附接到选择性释放金属部分。

9. 发明授权

US5280139A Selectively releasing conductive runner and substrate assembly 失效
标题翻译：选择性地释放导电流道和基板组件
公开(公告)号：US5280139A
公开(公告)日：1994-01-18
申请号：US930498
申请日：1992-08-17
申请人： Anthony B. Suppelsa , William B. Mullen, III , Glenn F. Urbish
发明人： Anthony B. Suppelsa , William B. Mullen, III , Glenn F. Urbish
IPC分类号： H01L21/60 , H05K1/00 , H05K1/03 , H05K3/40
CPC分类号： H01L24/81 , H05K3/4092 , H01L2224/16 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01056 , H01L2924/01057 , H01L2924/01063 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/15151 , H01L2924/15173 , H05K1/0306 , H05K1/0393
摘要： A selectively releasing runner and substrate assembly 10 comprises a plurality of conductive runners 16 adhered to a substrate 12, a portion 18 of at least some of the conductive runners 16 have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress.
摘要翻译：选择性地释放流道和基底组件10包括粘附到基底12的多个导电流道16，至少一些导电流道16的部分18对基底具有较低的粘附性，以便当基底上选择性地释放导电流道时，受到预定的应力。

10. 发明授权

US4626309A Selective bonding interconnection mask 失效
标题翻译：选择性粘接互连面罩
公开(公告)号：US4626309A
公开(公告)日：1986-12-02
申请号：US627127
申请日：1984-07-02
申请人： William B. Mullen, III , James H. Grotelueschen , Robert Henschel
发明人： William B. Mullen, III , James H. Grotelueschen , Robert Henschel
IPC分类号： C09J5/00 , H05K1/02 , H05K1/03 , H05K3/00 , H05K3/28 , H05K3/32 , B32B31/04 , B32B31/12
CPC分类号： H05K3/0061 , C09J5/00 , H05K1/0271 , H05K1/0306 , H05K2201/0999 , H05K2203/0191 , H05K3/281 , H05K3/321 , Y10T29/49126 , Y10T428/24289 , Y10T428/24331
摘要： An interconnection mask which is sandwiched between two members to be bonded together is comprised of a thin sheet of preselected material which has a plurality of apertures therein which are positioned, sized, and shaped to define the common bonding areas between the two members whereby structural failures induced by bonding and loading characteristics of the two members are minimized. A method for making an apparatus which utilizes the interconnection mask comprises the steps of preparing a mask of preselected material having a plurality of apertures therein, each aperture being positioned, sized and shaped to define a common bonding area between first and second members of the apparatus whereby the structural failures induced by the bonding and loading characteristics of the two members are minimized; placing a layer of bonding material on a surface of the first member; placing the interconnection mask over the layer of bonding material; placing the second member over the mask; bonding the first and second members together at each common bonding area defined by the apertures in the mask.
摘要翻译：被夹在两个待接合的构件之间的互连掩模由预选材料薄片组成，其中具有多个孔，其中定位，大小和成形以限定两个构件之间的共同接合区域，从而结构故障通过两个构件的结合和加载特性引起的最小化。制造利用所述互连掩模的装置的方法包括以下步骤：制备其中具有多个孔的预选材料的掩模，每个孔被定位，尺寸和形状以在所述装置的第一和第二构件之间限定公共粘合区域由此两个构件的结合和加载特性引起的结构失效最小化; 在所述第一构件的表面上放置一层接合材料; 将互连掩模放置在结合材料层上; 将第二个成员放在面罩上; 在由掩模中的孔限定的每个公共接合区域处将第一和第二构件结合在一起。

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