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1. 发明授权

US5540379A Soldering process 失效
标题翻译：焊接工艺
公开(公告)号：US5540379A
公开(公告)日：1996-07-30
申请号：US236611
申请日：1994-05-02
申请人： Vahid Kazem-Goudarzi , Henry F. Liebman , Kingshuk Banerji , William B. Mullen, III , Edwin L. Bradley, III
发明人： Vahid Kazem-Goudarzi , Henry F. Liebman , Kingshuk Banerji , William B. Mullen, III , Edwin L. Bradley, III
IPC分类号： B23K35/02 , B23K35/26 , H05K3/34
CPC分类号： B23K35/0244 , B23K35/26 , H05K3/3484 , B23K35/025 , H05K2201/0272 , H05K2203/043 , H05K3/3463
摘要： A soldering process using two different types of solder alloys is disclosed. The first solder alloy (115) undergoes a solid-to-liquid transition at a first temperature. The second solder alloy (120) undergoes this solid-to-liquid transition at a second temperature, the second temperature being greater than the first temperature. The soldering composition is deposited (20) on a substrate (100) having solderable portions (105) and is heated to a temperature that is above the first temperature but below the second temperature (32). During this time, the first solder alloy liquifies, while the second solder alloy remains solid. The soldering composition is subsequently cooled (40) to solidify the first solder material. A part or electronic component is added (80) to the solidified solder material and the solder materials is again heated above the second temperature (30) in order to reflow the solder and form a metallurgical bond between the substrate and the electronic component.
摘要翻译：公开了使用两种不同类型的焊料合金的焊接工艺。第一焊料合金（115）在第一温度下经历固 - 液转变。第二焊料合金（120）在第二温度下经历该固 - 液转变，第二温度大于第一温度。将焊接组合物沉积在具有可焊接部分（105）的基底（100）上，并被加热到高于第一温度但低于第二温度（32）的温度。在此期间，第一焊料合金液化，而第二焊料合金保持固体。焊接组合物随后被冷却（40）以固化第一焊料材料。向固化的焊料材料添加部件或电子部件（80），并且焊料材料再次被加热到高于第二温度（30）以便回流焊料并在基板和电子部件之间形成冶金结合。

2. 发明授权

US5427865A Multiple alloy solder preform 失效
标题翻译：多合金焊料预制件
公开(公告)号：US5427865A
公开(公告)日：1995-06-27
申请号：US236614
申请日：1994-05-02
申请人： William B. Mullen, III , Kingshuk Banerji , Edwin L. Bradley, III , Vahid Kazem-Goudarzi
发明人： William B. Mullen, III , Kingshuk Banerji , Edwin L. Bradley, III , Vahid Kazem-Goudarzi
IPC分类号： B23K35/02 , B23K35/14 , B23K35/26 , H05K3/34 , B22F7/02
CPC分类号： B23K35/0244 , B23K35/262 , H05K3/3484 , H05K2201/0272 , H05K2203/0338 , H05K2203/043 , H05K3/3452 , H05K3/3463 , Y10T428/12014 , Y10T428/12028 , Y10T428/12063 , Y10T428/12097 , Y10T428/12104 , Y10T428/1216
摘要： A solder preform (250) has solder particles of one alloy (210) arranged within a matrix of a second solder alloy (200). This arrangement forms a structure having the desired predetermined shape of the solder preform. The solder particles comprise one or more of the following elements: tin, lead, bismuth, indium, copper, antimony, cadmium, arsenic, aluminum, gallium, gold, silver. The particles have a predetermined melting temperature. The second solder alloy is compositionally distinct from the solder particles, and has a melting temperature that is lower than the melting temperature of the solder particles. The solder particles may comprise about 88% by weight of the solder preform, and the second solder alloy comprises about 12% by weight of the preform.
摘要翻译：焊料预制件（250）具有布置在第二焊料合金（200）的基体内的一个合金（210）的焊料颗粒。这种布置形成了具有所需预定形状的焊料预制件的结构。焊料颗粒包括以下元素中的一种或多种：锡，铅，铋，铟，铜，锑，镉，砷，铝，镓，金，银。颗粒具有预定的熔融温度。第二焊料合金在组成上不同于焊料颗粒，并且具有低于焊料颗粒的熔化温度的熔化温度。焊料颗粒可以包含约88重量％的焊料预制件，第二焊料合金占预制件的约12重量％。

3. 发明授权

US5415944A Solder clad substrate 失效
标题翻译：焊接基板
公开(公告)号：US5415944A
公开(公告)日：1995-05-16
申请号：US236615
申请日：1994-05-02
申请人： Vahid Kazem-Goudarzi , Edwin L. Bradley, III , Kingshuk Banerji , Henry F. Liebman
发明人： Vahid Kazem-Goudarzi , Edwin L. Bradley, III , Kingshuk Banerji , Henry F. Liebman
IPC分类号： B22F1/00 , B23K35/02 , B23K35/26 , C22C1/04 , H05K3/12 , H05K3/34 , B22F7/00 , H01L23/02
CPC分类号： H05K3/3484 , B22F1/0003 , B23K35/0244 , B23K35/262 , C22C1/04 , H05K2201/0215 , H05K2201/0272 , H05K2203/043 , H05K2203/0568 , H05K3/1216 , H05K3/3452 , H05K3/3463 , Y10T428/12014 , Y10T428/12028 , Y10T428/12063 , Y10T428/12097 , Y10T428/12104 , Y10T428/1216
摘要： A solder-clad printed circuit board (100) has solder particles of one alloy (120) arranged within a matrix of a second solder alloy (115). This arrangement forms a flat structure that is alloyed to the solder pads (105) on the substrate. The solder particles (120) have a predetermined melting temperature and are made from one or more of the following elements: tin, lead, bismuth, indium, copper, antimony, cadmium, arsenic, aluminum, gallium, gold, silver. The second solder alloy (115) is compositionally distinct from the solder particles, and has a melting temperature that is lower than the melting temperature of the solder particles. The solder particles may comprise about 88% by weight, and the second solder alloy may comprise about 12% by weight of the solder cladding.
摘要翻译：焊料包覆印刷电路板（100）具有布置在第二焊料合金（115）的基体内的一种合金（120）的焊料颗粒。这种布置形成了与衬底上的焊盘（105）合金化的平坦结构。焊料颗粒（120）具有预定的熔融温度，并且由以下元素中的一种或多种制成：锡，铅，铋，铟，铜，锑，镉，砷，铝，镓，金，银。第二焊料合金（115）在组成上不同于焊料颗粒，并且具有低于焊料颗粒的熔化温度的熔化温度。焊料颗粒可以包含约88重量％，并且第二焊料合金可以包含约12重量％的焊料包层。

4. 发明授权

US5429293A Soldering process 失效
标题翻译：焊接工艺
公开(公告)号：US5429293A
公开(公告)日：1995-07-04
申请号：US358295
申请日：1994-12-19
申请人： Edwin L. Bradley, III , Kingshuk Banerji , Vahid Kazem-Goudarzi
发明人： Edwin L. Bradley, III , Kingshuk Banerji , Vahid Kazem-Goudarzi
IPC分类号： B23K35/02 , B23K35/26 , H05K3/12 , H05K3/34
CPC分类号： H05K3/3463 , B23K35/025 , B23K35/26 , H05K3/3484 , B23K2201/04 , B23K2201/12 , H05K2201/035 , H05K2201/10992 , H05K2203/043 , H05K3/1216
摘要： A soldering process uses two or more different solder alloys. A first solder alloy (115) that undergoes a solid-to-liquid transition at a first temperature is coated (20) onto the solderable surfaces (105) of a printed circuit board (100). A solder paste (120) that undergoes this solid-to-liquid transition at a temperature greater than the first temperature is deposited on the coated solderable potions, and is heated to a temperature that is above the first temperature but below the second temperature. During this time, the first solder alloy liquifies, while the solder paste does not. The first solder alloy wets to the individual particles in the solder paste, and alloys to the solderable surfaces and the solder particles in the solder paste. The soldering composition is subsequently cooled (40) to solidify the first solder material, forming a solid and substantially planar coating on the solderable potions of the printed circuit board.
摘要翻译：焊接工艺使用两种或更多种不同的焊料合金。在第一温度下经历固 - 液过渡的第一焊料合金（115）涂覆（20）到印刷电路板（100）的可焊接表面（105）上。在大于第一温度的温度下经历该固 - 液过渡的焊膏（120）沉积在涂覆的可焊接部分上，并被加热到高于第一温度但低于第二温度的温度。在此期间，第一焊料合金液化，而锡膏不发生。第一焊料合金润湿焊锡膏中的各个颗粒，并将其焊接到可焊接表面和焊膏中的焊料颗粒。焊接组合物随后被冷却（40）以固化第一焊料材料，在印刷电路板的可焊接部分上形成固体和基本上平面的涂层。

5. 发明授权

US5623127A Single alloy solder clad substrate 失效
标题翻译：单合金焊包覆基板
公开(公告)号：US5623127A
公开(公告)日：1997-04-22
申请号：US348427
申请日：1994-12-02
申请人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
发明人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
IPC分类号： B23K35/14 , B23K35/26 , H05K3/24 , H05K3/34 , H05K1/02
CPC分类号： B23K35/262 , H05K3/3484 , H05K2203/043 , H05K3/3463
摘要： A solder clad printed circuit board (100) consists of an electrically insulating substrate that has copper circuit traces (105), portions of which are solderable. A substantially planar layer (120) of a soldering composition is fused to the solderable traces, to form a solder pad that is not domed. The layer is composed of a mass of off-eutectic solder particles (115) that are fused together to form an agglomeration (120) having a porous structure. The solder particles are fused together by heating the off-eutectic solder to a temperature that is between the solidus temperature and the liquidus temperature of the solder. The solder is then cooled below the solidus temperature to solidify it.
摘要翻译：焊料包覆印刷电路板（100）由具有铜电路迹线（105）的电绝缘基板组成，其一部分是可焊接的。焊接组合物的基本平坦的层（120）被熔合到可焊接迹线，以形成不是圆顶的焊盘。该层由大量的非共熔焊料颗粒（115）组成，它们被熔合在一起以形成具有多孔结构的附聚物（120）。通过将非共晶焊料加热到固相线温度和焊料的液相线温度之间的温度将焊料颗粒熔合在一起。然后将焊料冷却至固相线温度以使其固化。

6. 发明授权

US5293067A Integrated circuit chip carrier 失效
标题翻译：集成电路芯片载体
公开(公告)号：US5293067A
公开(公告)日：1994-03-08
申请号：US898231
申请日：1992-06-12
申请人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
发明人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
IPC分类号： H01L23/12 , H01L21/56 , H01L23/32 , H01L23/498 , H01L23/02
CPC分类号： H01L23/49827 , H01L21/563 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01004 , H01L2924/15311
摘要： An integrated circuit chip carrier assembly, comprising a semiconductor device (10) having interconnection pads (14) disposed on an active surface (12) of the device. The device (10) is attached by means of electrically conducting bumps (26) to a circuitry pattern (18) on a first side of a circuit carrying substrate (16). The substrate is typically an aramid reinforced organic resin, such as epoxy. The circuitry (18, 20) is electrically connected by conductive through-holes (22) to an array of solder pads on a second side of the substrate. Some or all of the through-holes (22) are covered by the device. The overall length and width of the circuit carrying substrate (16) are each a maximum of about 0.15 inches greater than the equivalent dimensions of the device (10), creating a carrier that is only slightly larger than the semiconductor device itself.
摘要翻译：一种集成电路芯片载体组件，包括具有布置在所述装置的有效表面（12）上的互连焊盘（14）的半导体器件（10）。装置（10）通过导电凸块（26）连接到电路承载衬底（16）的第一侧上的电路图案（18）。基底通常是芳族聚酰胺增强的有机树脂，例如环氧树脂。电路（18,20）通过导电通孔（22）电连接到衬底的第二侧上的焊盘阵列。一些或全部通孔（22）被装置覆盖。电路承载基板（16）的总长度和宽度各自最大大约为装置（10）的等效尺寸约0.15英寸，从而形成仅略大于半导体装置本身的载体。

7. 发明授权

US5311059A Backplane grounding for flip-chip integrated circuit 失效
标题翻译：背板接地用于倒装芯片集成电路
公开(公告)号：US5311059A
公开(公告)日：1994-05-10
申请号：US825367
申请日：1992-01-24
申请人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
发明人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L23/14 , H01L23/24 , H01L23/58
CPC分类号： H01L23/585 , H01L21/56 , H01L21/563 , H01L23/145 , H01L23/24 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2924/01014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15151 , H01L2924/15311
摘要： A semiconductor device package comprises a substrate (20) having a metallization pattern (22) on at least one surface, and a semiconductor device (10) having an active surface (12) and a grounded surface (14) on opposed sides. The semiconductor device is electrically attached to the substrate metallization pattern with the active surface (12) facing the substrate. A polymeric underfill material (30) substantially fills the space between the semiconductor device and the substrate. An electrically conductive material (35) covers the exposed grounded surface (14) of the semiconductor device and at least a portion of the metallization pattern (22), providing electrical connection between the grounded surface of the semiconductor and the metallization pattern (22) on the substrate.
摘要翻译：半导体器件封装包括在至少一个表面上具有金属化图案（22）的衬底（20）和在相对侧上具有有源表面（12）和接地表面（14）的半导体器件（10）。半导体器件电连接到衬底金属化图案，其中有源表面（12）面向衬底。聚合物底部填充材料（30）基本上填充半导体器件和衬底之间的空间。导电材料（35）覆盖半导体器件的暴露的接地表面（14）和金属化图案（22）的至少一部分，在半导体的接地表面和金属化图案（22）之间提供电连接，底物。

8. 发明授权

US5446625A Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface 失效
标题翻译：芯片载体具有在一个表面上镀金并且在另一个表面上没有金的铜图案
公开(公告)号：US5446625A
公开(公告)日：1995-08-29
申请号：US365988
申请日：1994-12-28
申请人： Glenn F. Urbish , William B. Mullen, III , Kingshuk Banerji
发明人： Glenn F. Urbish , William B. Mullen, III , Kingshuk Banerji
IPC分类号： H01L23/31 , H01L23/498 , H05K7/02 , H01L23/28 , H05K1/18
CPC分类号： H01L23/498 , H01L23/3121 , H01L2224/05644 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L24/45 , H01L24/48 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311
摘要： A chip carrier (20) includes a substrate (11) having a first copper pattern (12) deposited on a first surface (13), and a second copper pattern (14) deposited on a second surface (16). The second copper pattern (14) is plated with a metallic material to form wire bondable areas (18) on the second copper pattern (14), however, the first copper pattern (12) is substantially devoid of the metallic material. A device (21) is wire bonded to the wire bondable areas (18) of the second copper pattern (14), and a protective covering (23) covers the wire bondable areas (18).
摘要翻译：芯片载体（20）包括具有沉积在第一表面（13）上的第一铜图案（12）的基底（11）和沉积在第二表面（16）上的第二铜图案。第二铜图案（14）镀有金属材料，以在第二铜图案（14）上形成可焊接区域（18），然而，第一铜图案（12）基本上不含金属材料。将装置（21）引线接合到第二铜图案（14）的可焊接区域（18），并且保护覆盖物（23）覆盖可焊接区域（18）。

9. 发明授权

US5573602A Solder paste 失效
标题翻译：焊膏
公开(公告)号：US5573602A
公开(公告)日：1996-11-12
申请号：US358489
申请日：1994-12-19
申请人： Kingshuk Banerji , Edwin L. Bradley, III
发明人： Kingshuk Banerji , Edwin L. Bradley, III
IPC分类号： B23K35/02 , B23K35/14 , B23K35/26 , H05K3/34 , B23K35/34
CPC分类号： B23K35/262 , B23K35/0244 , B23K35/025 , H05K3/3484 , H05K2201/0218 , H05K3/3463 , Y10T428/12181
摘要： A solder paste is made from solder powder having two different alloys. The individual particles in the solder powder consist of a low melting solder coating (115) that surrounds a nucleus (120) of a higher melting solder. The low melting solder is compositionally distinct from the higher melting solder. The particles are suspended in a matrix of a solder paste vehicle, which may also contain a fluxing agent. In one embodiment of the invention, the low melting solder is an alloy of 43% tin, 43% lead and 14% bismuth, and the higher melting solder is an alloy of 52% tin, and 48% bismuth.
摘要翻译：焊膏由具有两种不同合金的焊料粉末制成。焊料粉末中的单个颗粒由围绕较高熔点焊料的核（120）的低熔点焊料涂层（115）组成。低熔点焊料在组成上不同于较高熔点的焊料。颗粒悬浮在焊膏载体的基质中，焊膏载体也可以含有助熔剂。在本发明的一个实施例中，低熔点焊料是43％锡，43％铅和14％铋的合金，而较高熔点的焊料是52％锡和48％铋的合金。

10. 发明授权

US5166774A Selectively releasing conductive runner and substrate assembly having non-planar areas 失效
标题翻译：选择性地释放具有非平面区域的导电流道和基底组件
公开(公告)号：US5166774A
公开(公告)日：1992-11-24
申请号：US593410
申请日：1990-10-05
申请人： Kingshuk Banerji , Anthony B. Suppelsa , William B. Mullen, III.
发明人： Kingshuk Banerji , Anthony B. Suppelsa , William B. Mullen, III.
IPC分类号： H01L21/48 , H01L23/498 , H05K3/40
CPC分类号： H01L21/4839 , H01L23/49861 , H05K3/4092 , H01L2224/16245
摘要： A selectively releasing runner and substrate assembly 100 comprises a plurality of conductive runners 116 adhered to a substrate 112, a portion 118 of at least some of the conductive runners 116 have non-planar areas with the substrate 112. Additionally the portion 118 has a lower adhesion to the substrate for selectively releasing the conductive runner 118 from the substrate 112 when subjected to a predetermined stress.
摘要翻译：选择性地释放流道和基底组件100包括粘附到基底112的多个导电流道116，至少一些导电流道116的部分118具有与基底112的非平面区域。另外，部分118具有较低的对基板的粘附，用于当受到预定应力时从基板112选择性地释放导电流道118。

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