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1. 发明授权

US5641980A Device having a high concentration region under the channel 失效
标题翻译：在通道下具有高浓度区域的奇偶装置
公开(公告)号：US5641980A
公开(公告)日：1997-06-24
申请号：US557558
申请日：1995-11-14
申请人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
发明人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
IPC分类号： H01L29/40 , H01L21/336 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66757 , H01L27/1203 , H01L29/78606 , H01L29/78609 , H01L29/78621
摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.
摘要翻译：本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'））。在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

2. 发明授权

US5926703A LDD device having a high concentration region under the channel 失效
标题翻译： LDD器件在通道下方具有高浓度区域
公开(公告)号：US5926703A
公开(公告)日：1999-07-20
申请号：US785277
申请日：1997-01-21
申请人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
发明人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
IPC分类号： H01L29/40 , H01L21/336 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/786 , H01L21/44
CPC分类号： H01L29/66757 , H01L27/1203 , H01L29/78606 , H01L29/78609 , H01L29/78621
摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.
摘要翻译：本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'））。在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

3. 发明授权

US06727552B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06727552B2
公开(公告)日：2004-04-27
申请号：US10062462
申请日：2002-02-05
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

4. 发明授权

US06649976B2 Semiconductor device having metal silicide film and manufacturing method thereof 失效
公开(公告)号：US06649976B2
公开(公告)日：2003-11-18
申请号：US09982777
申请日：2001-10-22
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L2976
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

5. 发明授权

US6118154A Input/output protection circuit having an SOI structure 失效
标题翻译：具有SOI结构的输入/输出保护电路
公开(公告)号：US6118154A
公开(公告)日：2000-09-12
申请号：US947345
申请日：1997-10-08
申请人： Yasuo Yamaguchi , Hirotoshi Sato , Yasuo Inoue , Toshiaki Iwamatsu
发明人： Yasuo Yamaguchi , Hirotoshi Sato , Yasuo Inoue , Toshiaki Iwamatsu
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/786 , H01L23/60
CPC分类号： H01L27/0251
摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.
摘要翻译： I / O保护电路包括连接在输入端和电源线之间的P沟道MOS晶体管和连接在输入端和接地线之间的N沟道MOS晶体管。两个晶体管的栅极电极浮起来。晶体管可以被栅极二极管代替。此外，栅电极可以由与用于场屏蔽的栅电极相同的层形成。

6. 发明授权

US6051494A Semiconductor device having metal silicide film 失效
标题翻译：具有金属硅化物膜的半导体器件
公开(公告)号：US6051494A
公开(公告)日：2000-04-18
申请号：US855259
申请日：1997-05-13
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L21/26586 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
摘要翻译：可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。因此，在源极区域中，可以形成更厚的硅化钛膜。

7. 发明授权

US5128732A Stacked semiconductor device 失效
标题翻译：堆叠半导体器件
公开(公告)号：US5128732A
公开(公告)日：1992-07-07
申请号：US199439
申请日：1988-05-27
申请人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue , Yasuo Yamaguchi
发明人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue , Yasuo Yamaguchi
IPC分类号： H01L27/06
CPC分类号： H01L27/0688
摘要： A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer. A semiconductor for forming the upper layer of a semiconductor having the same crystal axis as the lower layer of a semiconductor is deposited in the opening of the upper insulating layer so that satisfactory lateral epitaxial growth will occur over the insulating layer.
摘要翻译：叠层半导体器件具有三维交替层的半导体元件和绝缘层，每个绝缘层将形成在单晶半导体衬底上的相邻的半导体元件的上层和下层电绝缘。分别在绝缘层中形成的开口中沉积半导体，以形成分别在绝缘层上分别与单晶半导体衬底相同的晶轴的单晶半导体层，并分别形成多个半导体元件。通过上绝缘层形成的开口到达同一上绝缘层正下方的半导体元件的下层，并形成在与通过同一上绝缘层正下方的下绝缘层形成的开口水平间隔开的位置处。用于形成具有与半导体的下层相同的晶轴的半导体的上层的半导体被沉积在上绝缘层的开口中，使得在绝缘层上将发生令人满意的横向外延生长。

8. 发明授权

US4982102A Apparatus for detecting three-dimensional configuration of object employing optical cutting method 失效
标题翻译：使用光学切割方法检测物体的三维构型的装置
公开(公告)号：US4982102A
公开(公告)日：1991-01-01
申请号：US424924
申请日：1989-10-23
申请人： Yasuo Inoue , Yasuo Yamaguchi
发明人： Yasuo Inoue , Yasuo Yamaguchi
IPC分类号： G01B11/24 , G01B11/25
CPC分类号： G01B11/25
摘要： Disclosed is an apparatus for detecting the three-dimensional configuration of an object employing an optical cutting method. A light projector pulse-flashes slit-shaped light and causes the light to scan an object at a predetermined speed. An image sensor having a plurality of pixels is disposed in opposition to the object. An optical system forms on the image sensor an image of an optical cutting line formed on the surface of the object by the light. Counters each count the number of pulses of the image of the optical cutting line that has been detected by each pixel. A time calculator calculates the time at which the image has passed each of the pixels, on the basis of the counted numbers of pulses. A configuration calculator calculates the three-dimensional configuration of the object on the basis of the calculated passage time and the scanning speed of the slit-shaped light. Because the counted numbers of pulses, which are each indicative of the period of time required for the image of the optical cutting line to pass each pixel, are used to calculate the passage time, there is no need to provide a data bus to transmit time data with respect to the each pixel. Thus, the apparatus has simple wiring arrangement, and can be manufactured with ease.
摘要翻译：公开了一种使用光学切割方法检测物体的三维构造的装置。光投射器脉冲闪烁狭缝状光，并使光以预定速度扫描物体。具有多个像素的图像传感器设置成与物体相对。光学系统在图像传感器上形成通过光形成在物体表面上的光学切割线的图像。计数器各自计数由每个像素检测的光学切割线的图像的脉冲数。时间计算器基于计数的脉冲数来计算图像已经通过每个像素的时间。配置计算器基于所计算的通过时间和狭缝状光的扫描速度来计算物体的三维配置。由于计数通过时间的光学切割线的图像所需的时间周期的脉冲的计数数据用于计算通过时间，因此不需要提供数据总线来传送时间相对于每个像素的数据。因此，该装置具有简单的布线布置，并且可以容易地制造。

9. 发明授权

US07001822B2 Semiconductor device formed on insulating layer and method of manufacturing the same 失效
公开(公告)号：US07001822B2
公开(公告)日：2006-02-21
申请号：US10682124
申请日：2003-10-10
申请人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
发明人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/76297 , H01L21/26586 , H01L21/764 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L29/78633 , H01L29/78654
摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

10. 发明授权

US06653656B2 Semiconductor device formed on insulating layer and method of manufacturing the same 失效
标题翻译：绝缘层上形成的半导体器件及其制造方法
公开(公告)号：US06653656B2
公开(公告)日：2003-11-25
申请号：US10336758
申请日：2003-01-06
申请人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
发明人： Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
IPC分类号： H01L2904
CPC分类号： H01L21/76297 , H01L21/26586 , H01L21/764 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L29/78633 , H01L29/78654
摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
摘要翻译：在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。在该半导体器件中，半导体层的上侧部分是圆形的。由此，可以防止半导体层的上侧部分的电场集中。结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。因此，不会在制造过程中引起缺点。

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