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1. 发明公开

US20240387239A1 MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 审中-公开
公开(公告)号：US20240387239A1
公开(公告)日：2024-11-21
申请号：US18209488
申请日：2023-06-14
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Tsang Chen , Chia-Ching Lin , Wen-Liang Huang
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/76229 , H01L21/823431 , H01L21/823481 , H01L29/66795
摘要： A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.

2. 发明授权

US09136140B2 Patterning method 有权
标题翻译：图案化方法
公开(公告)号：US09136140B2
公开(公告)日：2015-09-15
申请号：US14025524
申请日：2013-09-12
申请人： United Microelectronics Corp.
发明人： Wen-Liang Huang , Chia-Hung Lin , Chun-Chi Yu
IPC分类号： H01L21/00 , H01L21/308
CPC分类号： H01L21/3086 , H01L21/0271 , H01L21/0337 , H01L21/3088
摘要： A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.
摘要翻译：提供了图案化方法。首先，在基板上形成材料层。此后，在材料层上形成多个定向自组装（DSA）图案。之后，通过使用单个光刻工艺形成图案化的光致抗蚀剂层。图案化的光致抗蚀剂层覆盖DSA图案的第一部分并且暴露DSA图案的第二部分。此外，通过蚀刻工艺，使用图案化的光致抗蚀剂层和DSA图案的第二部分作为掩模来对材料层进行图案化。

3. 发明授权

US10916636B2 Method of forming gate 有权
公开(公告)号：US10916636B2
公开(公告)日：2021-02-09
申请号：US16276642
申请日：2019-02-15
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Tsang Chen , Wen-Liang Huang , Chun-Chi Yu
IPC分类号： H01L29/66 , H01L21/28 , H01L21/027 , H01L29/49
摘要： A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.

4. 发明授权

US09506965B2 Alternately arranged overlay marks having asymmetric spacing and measurement thereof 有权
标题翻译：具有不对称间隔和其测量的交替布置的覆盖标记
公开(公告)号：US09506965B2
公开(公告)日：2016-11-29
申请号：US13674704
申请日：2012-11-12
申请人： United Microelectronics Corp.
发明人： Kuo-Chun Huang , Chien-Hao Chen , Wen-Liang Huang
IPC分类号： G03F1/42 , G03F1/38 , G01R27/26 , G01R27/02 , G03F7/20
CPC分类号： G01R27/2605 , G01R27/02 , G03F1/38 , G03F1/42 , G03F7/70616 , G03F7/70633 , G06T2207/30148
摘要： An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
摘要翻译：提供了包括至少一个第一重叠标记和至少一个第二重叠标记的重叠标记。第一覆盖标记包括多个第一条和交替布置的多个第一空间，并且第一空间不是恒定的。第二覆盖标记包括多个第二条和交替排列的多个第二空间，第二空间是恒定的。此外，第二覆盖标记部分地与第一覆盖标记重叠。

5. 发明申请

US20140132283A1 OVERLAY MARK AND MEASUREMENT METHOD THEREOF 有权
标题翻译：覆盖标记及其测量方法
公开(公告)号：US20140132283A1
公开(公告)日：2014-05-15
申请号：US13674704
申请日：2012-11-12
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuo-Chun Huang , Chien-Hao Chen , Wen-Liang Huang
IPC分类号： G01R27/26 , G01R27/02
CPC分类号： G01R27/2605 , G01R27/02 , G03F1/38 , G03F1/42 , G03F7/70616 , G03F7/70633 , G06T2207/30148
摘要： An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
摘要翻译：提供了包括至少一个第一重叠标记和至少一个第二重叠标记的重叠标记。第一覆盖标记包括多个第一条和交替布置的多个第一空间，并且第一空间不是恒定的。第二覆盖标记包括多个第二条和交替排列的多个第二空间，第二空间是恒定的。此外，第二覆盖标记部分地与第一覆盖标记重叠。

6. 发明公开

US20240379670A1 Semiconductor device and fabricating method of the same 审中-公开
公开(公告)号：US20240379670A1
公开(公告)日：2024-11-14
申请号：US18206609
申请日：2023-06-06
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ya-Ting Hu , Chih-Yi Wang , Yao-Jhan Wang , Wei-Che Chen , Kun-Szu Tseng , Yun-Yang He , Wen-Liang Huang , Lung-En Kuo , Po-Tsang Chen , Po-Chang Lin , Ying-Hsien Chen
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/0886 , H01L21/76229
摘要： A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

7. 发明授权

US09304389B2 Photomask and fabrication method thereof 有权
标题翻译：光掩模及其制造方法
公开(公告)号：US09304389B2
公开(公告)日：2016-04-05
申请号：US14067986
申请日：2013-10-31
申请人： UNITED MICROELECTRONICS CORP.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
IPC分类号： G03F1/68 , G03F1/00
CPC分类号： G03F1/00 , G03F1/50 , G03F1/68
摘要： A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
摘要翻译：提供包括第一不透明图案和第二不透明图案的光掩模。第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案隔开。换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。

8. 发明申请

US20150118602A1 PHOTOMASK AND FABRICATION METHOD THEREOF 有权
标题翻译：光电及其制造方法
公开(公告)号：US20150118602A1
公开(公告)日：2015-04-30
申请号：US14067986
申请日：2013-10-31
申请人： UNITED MICROELECTRONICS CORP.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
IPC分类号： G03F1/00 , G03F7/20 , G03F1/68
CPC分类号： G03F1/00 , G03F1/50 , G03F1/68
摘要： A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
摘要翻译：提供包括第一不透明图案和第二不透明图案的光掩模。第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案间隔开。换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。

9. 发明授权

US08954919B1 Calculation method for generating layout pattern in photomask 有权
标题翻译：在光掩模中生成布局图案的计算方法
公开(公告)号：US08954919B1
公开(公告)日：2015-02-10
申请号：US14069391
申请日：2013-11-01
申请人： United Microelectronics Corp.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang , Yu-Chin Huang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.
摘要翻译：用于生成光掩模中的布局图案的计算方法至少包括以下步骤。将包括分布在平面中的几个几何图案的二维设计布局提供给计算机系统。计算机系统用于标记几何图案的部分并且生成至少一个标记的几何图案和至少一个未标记的几何图案。然后通过计算机系统模拟和校正标记的几何图案，以生成3维设计布局。通过模拟和校正，标记的几何图案和未标记的几何图案沿着与平面正交的轴线交替布置。 3-D设计布局随后输出到制版系统。

10. 发明申请

US20200266285A1 METHOD OF FORMING GATE 审中-公开
公开(公告)号：US20200266285A1
公开(公告)日：2020-08-20
申请号：US16276642
申请日：2019-02-15
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Tsang Chen , Wen-Liang Huang , Chun-Chi Yu
IPC分类号： H01L29/66 , H01L21/027 , H01L21/28
摘要： A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.

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