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1. 发明授权

US10777420B1 Etching back method 有权
公开(公告)号：US10777420B1
公开(公告)日：2020-09-15
申请号：US16286495
申请日：2019-02-26
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuan-Ying Lai , Chang-Mao Wang , Hsin-Yu Hsieh
IPC分类号： H01L21/311 , H01L21/768 , H01L21/02 , H01L21/306 , H01L21/31 , H01L21/3065 , H01L21/3105 , H01L21/04 , H01L21/308
摘要： A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

2. 发明申请

US20220392768A1 PATTERNING METHOD AND OVERLAY MESUREMENT METHOD 有权
公开(公告)号：US20220392768A1
公开(公告)日：2022-12-08
申请号：US17341183
申请日：2021-06-07
申请人： United Microelectronics Corp.
发明人： Yi Jing Wang , Chia-Chang Hsu , Chien-Hao Chen , Chang-Mao Wang , Chun-Chi Yu
IPC分类号： H01L21/033 , H01L21/311 , H01L23/544 , H01L21/66 , G03F7/20
摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

3. 发明授权

US11488829B1 Method of forming a semiconductor device 有权
公开(公告)号：US11488829B1
公开(公告)日：2022-11-01
申请号：US17337457
申请日：2021-06-03
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuan-Ying Lai , Hsin-Yu Hsieh , Chang-Mao Wang , Chung-Yi Chiu
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/49
摘要： A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

4. 发明申请

US20220367192A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220367192A1
公开(公告)日：2022-11-17
申请号：US17337457
申请日：2021-06-03
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuan-Ying Lai , Hsin-Yu Hsieh , Chang-Mao Wang , Chung-Yi Chiu
IPC分类号： H01L21/28 , H01L29/49 , H01L21/3213
摘要： A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

5. 发明授权

US09304389B2 Photomask and fabrication method thereof 有权
标题翻译：光掩模及其制造方法
公开(公告)号：US09304389B2
公开(公告)日：2016-04-05
申请号：US14067986
申请日：2013-10-31
申请人： UNITED MICROELECTRONICS CORP.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
IPC分类号： G03F1/68 , G03F1/00
CPC分类号： G03F1/00 , G03F1/50 , G03F1/68
摘要： A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
摘要翻译：提供包括第一不透明图案和第二不透明图案的光掩模。第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案隔开。换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。

6. 发明申请

US20150118602A1 PHOTOMASK AND FABRICATION METHOD THEREOF 有权
标题翻译：光电及其制造方法
公开(公告)号：US20150118602A1
公开(公告)日：2015-04-30
申请号：US14067986
申请日：2013-10-31
申请人： UNITED MICROELECTRONICS CORP.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang
IPC分类号： G03F1/00 , G03F7/20 , G03F1/68
CPC分类号： G03F1/00 , G03F1/50 , G03F1/68
摘要： A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
摘要翻译：提供包括第一不透明图案和第二不透明图案的光掩模。第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案间隔开。换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。

7. 发明授权

US08954919B1 Calculation method for generating layout pattern in photomask 有权
标题翻译：在光掩模中生成布局图案的计算方法
公开(公告)号：US08954919B1
公开(公告)日：2015-02-10
申请号：US14069391
申请日：2013-11-01
申请人： United Microelectronics Corp.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang , Yu-Chin Huang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.
摘要翻译：用于生成光掩模中的布局图案的计算方法至少包括以下步骤。将包括分布在平面中的几个几何图案的二维设计布局提供给计算机系统。计算机系统用于标记几何图案的部分并且生成至少一个标记的几何图案和至少一个未标记的几何图案。然后通过计算机系统模拟和校正标记的几何图案，以生成3维设计布局。通过模拟和校正，标记的几何图案和未标记的几何图案沿着与平面正交的轴线交替布置。 3-D设计布局随后输出到制版系统。

8. 发明授权

US12147163B2 Method for correcting critical dimension measurements of lithographic tool 有权
公开(公告)号：US12147163B2
公开(公告)日：2024-11-19
申请号：US17528295
申请日：2021-11-17
申请人： UNITED MICROELECTRONICS CORP.
发明人： Hsin-Yu Hsieh , Kuan-Ying LAi , Chang-Mao Wang , Chien-Hao Chen , Chun-Chi Yu
IPC分类号： G03F7/00
CPC分类号： G03F7/70625
摘要： A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

9. 发明授权

US12106962B2 Patterning method and overlay measurement method 有权
公开(公告)号：US12106962B2
公开(公告)日：2024-10-01
申请号：US17341183
申请日：2021-06-07
申请人： United Microelectronics Corp.
发明人： Yi Jing Wang , Chia-Chang Hsu , Chien-Hao Chen , Chang-Mao Wang , Chun-Chi Yu
IPC分类号： H01L21/033 , G03F7/00 , G03F7/20 , H01L21/311 , H01L21/66 , H01L23/544
CPC分类号： H01L21/0337 , G03F7/2022 , G03F7/70633 , H01L21/31144 , H01L22/20 , H01L23/544
摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

10. 发明公开

US20230402288A1 METHOD OF REMOVING STEP HEIGHT ON GATE STRUCTURE 审中-公开
公开(公告)号：US20230402288A1
公开(公告)日：2023-12-14
申请号：US17857158
申请日：2022-07-04
申请人： UNITED MICROELECTRONICS CORP.
发明人： Yeh-Sheng Lin , Chang-Mao Wang , Chun-Chi Yu , Chung-Yi Chiu
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31111 , H01L21/76802 , H01L21/31144
摘要： A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

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