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1. 发明授权

US08954919B1 Calculation method for generating layout pattern in photomask 有权
标题翻译：在光掩模中生成布局图案的计算方法
公开(公告)号：US08954919B1
公开(公告)日：2015-02-10
申请号：US14069391
申请日：2013-11-01
申请人： United Microelectronics Corp.
发明人： En-Chiuan Liou , Sho-Shen Lee , Wen-Liang Huang , Chang-Mao Wang , Kai-Lin Chuang , Yu-Chin Huang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.
摘要翻译：用于生成光掩模中的布局图案的计算方法至少包括以下步骤。将包括分布在平面中的几个几何图案的二维设计布局提供给计算机系统。计算机系统用于标记几何图案的部分并且生成至少一个标记的几何图案和至少一个未标记的几何图案。然后通过计算机系统模拟和校正标记的几何图案，以生成3维设计布局。通过模拟和校正，标记的几何图案和未标记的几何图案沿着与平面正交的轴线交替布置。 3-D设计布局随后输出到制版系统。

2. 发明公开

US20240266210A1 Semiconductor circuit pattern and manufacturing method thereof 审中-公开
公开(公告)号：US20240266210A1
公开(公告)日：2024-08-08
申请号：US18116276
申请日：2023-03-01
申请人： UNITED MICROELECTRONICS CORP.
发明人： Yu-Chien Chung , Yu-Chin Huang , Chao-You Hung , Wei-Lin Liu
IPC分类号： H01L21/768 , H01L21/027 , H01L21/311 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76816 , H01L21/0274 , H01L21/31144 , H01L21/76831 , H01L21/76877 , H01L23/5226 , H01L23/528
摘要： The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.

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