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1. 发明申请

US20060292690A1 Method of making cell growth surface 审中-公开
标题翻译：细胞生长表面的方法
公开(公告)号：US20060292690A1
公开(公告)日：2006-12-28
申请号：US11471576
申请日：2006-06-21
申请人： Tzu-Ying Liu , Ing-Kae Wang , Sing-Ying Hsieh , Lewis Ho , Yu-Chi Wang , King-Ming Chang
发明人： Tzu-Ying Liu , Ing-Kae Wang , Sing-Ying Hsieh , Lewis Ho , Yu-Chi Wang , King-Ming Chang
IPC分类号： C12N5/06
CPC分类号： C12N5/0068 , C12M25/14 , C12N2533/70
摘要： The present invention discloses a three-dimensional porous growth surface made from polysaccharide material, especially the alginic acid, to enhance cell growth surface, promote cell adherence, immobilization and propagation, maintain surface structure integrity, enable programmable degradation, and thus increase cellular production. The present invention teaches several methods: a method to enhance the integrity of the growth surface by protecting the growth surface in a rigid solid support; a method of use for enhancing the performance of the surface; and a method of modifying a growth surface for eukaryotic and/or prokaryotic cells comprising the steps of increasing surface area by creating porous and 3-D structure, treating a surface to encourage cell attachment, promoting cell growth and proliferation, and disposing the growth surface in any conventional cell cultivating device. The growth surface is able to program degradation and release the cell/tissue mass after the culture is completed.
摘要翻译：本发明公开了一种由多糖材料特别是藻酸制成的三维多孔生长表面，以增强细胞生长表面，促进细胞粘附，固定和繁殖，保持表面结构完整性，实现可编程降解，从而增加细胞生产。本发明教导了几种方法：通过保护刚性固体支持物中的生长表面来增强生长表面完整性的方法; 用于增强表面性能的方法; 以及一种修饰真核细胞和/或原核细胞的生长表面的方法，包括以下步骤：通过产生多孔和3-D结构来增加表面积，处理表面以促进细胞附着，促进细胞生长和增殖，以及处置生长表面在任何常规的细胞培养装置中。生长表面能够在培养完成后编程降解和释放细胞/组织块。

2. 发明申请

US20050186669A1 Apparatus and method for preparing and culturing cells 审中-公开
标题翻译：用于制备和培养细胞的装置和方法
公开(公告)号：US20050186669A1
公开(公告)日：2005-08-25
申请号：US11059523
申请日：2005-02-17
申请人： Lewis Ho , Yu-Chi Wang , King-Ming Chang
发明人： Lewis Ho , Yu-Chi Wang , King-Ming Chang
IPC分类号： C12M1/02 , C12M1/04 , C12M1/12 , C12M1/24 , C12M1/34 , C12M1/40 , C12M1/42 , C12M3/00 , C12N5/02 , C12N5/06 , C12N5/08
CPC分类号： C12M23/14 , B01F11/0017 , C12M27/16
摘要： An apparatus and method for preparing and culturing cells includes a chamber having an inlet and an outlet for introducing culture medium and air. A cell growth substrate placed in the chamber for cells anchored or embedded. The preferred embodiment of invention claims a novel process for controlling the platform form to tilt at one end, to maintain the seesaw and rocking movement for cultured process. The seesaw movement or rocking movement efficiently the nutrition, carbon dioxide and oxygen transfer during cultured process for production of cellular protein products or harvesting the cells.
摘要翻译：用于制备和培养细胞的装置和方法包括具有用于引入培养基和空气的入口和出口的室。将细胞生长基质放置在室中用于锚定或嵌入的细胞。本发明的优选实施例要求用于控制平台形式在一端倾斜的新颖方法，以保持用于培养过程的跷跷板和摇摆运动。跷跷板运动或摇摆运动有效地在培养过程中的营养，二氧化碳和氧转移以产生细胞蛋白质产物或收获细胞。

3. 发明申请

US20080220599A1 Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices 有权
标题翻译：用于集成III-V化合物半导体器件的短栅极长度电极的制造方法
公开(公告)号：US20080220599A1
公开(公告)日：2008-09-11
申请号：US12153206
申请日：2008-05-15
申请人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L21/28
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785 , Y10S438/949 , Y10S438/95
摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
摘要翻译：公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

4. 发明申请

US20070278523A1 Structure and a method for monolithic integration of HBT, depletion-mode HEMT and enhancement-mode HEMT on the same substrate 审中-公开
标题翻译： HBT，耗尽型HEMT和增强型HEMT在同一衬底上单片集成的结构和方法
公开(公告)号：US20070278523A1
公开(公告)日：2007-12-06
申请号：US11446206
申请日：2006-06-05
申请人： Heng-Kuang Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Heng-Kuang Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L29/739
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785
摘要： An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT as well as passive devices, that enabling monolithic integration of a significant number of devices on a common substrate by a cost-effective way.
摘要翻译：公开了一种外延层结构和用于在公共衬底上制造HBT和HEMT的方法。外延层通常在一组HEMT层的顶部上包括一组HBT层。该方法可用于制造HBT，E模式HEMT和D模式HEMT以及无源器件，可以通过成本有效的方式在大量基板上实现大量器件的单片集成。

5. 发明授权

US10121300B2 Electric lock device and door including the same 有权
公开(公告)号：US10121300B2
公开(公告)日：2018-11-06
申请号：US15443691
申请日：2017-02-27
申请人： Yu-Chi Wang
发明人： Yu-Chi Wang
IPC分类号： G05B19/00 , G07C9/00 , G06K9/00
摘要： A door includes a door panel and an electric lock device including a solar energy module, a biometric verification module, a control module and an electric lock. The solar energy module converts solar energy into an electricity output. The biometric verification module receives a biometric input signal relative to a biometric feature, determines whether the biometric feature conforms with a set of pre-established data, and generates a conforming signal if the determination is affirmative. The control module receives the conforming signal to generate a control signal and an unlocking signal. The electric lock receives the control signal and the unlocking signal. The electric lock operates to unlock the door panel.

6. 发明授权

US06294116B1 Method for producing a crosslinked formed article 失效
标题翻译：交联成型体的制造方法
公开(公告)号：US06294116B1
公开(公告)日：2001-09-25
申请号：US09172073
申请日：1998-10-14
申请人： Hsi-Hsin Shih , Chien-Tsung Wu , Shihn-Juh Liou , Yu-Chi Wang , Chang-Ming Wong , Chi-Chou Huang , Chin-Chin Tsai
发明人： Hsi-Hsin Shih , Chien-Tsung Wu , Shihn-Juh Liou , Yu-Chi Wang , Chang-Ming Wong , Chi-Chou Huang , Chin-Chin Tsai
IPC分类号： B29C4420
CPC分类号： B29C47/0004 , B29C44/30 , B29C47/0021 , B29C47/0026 , B29C47/003 , B29C47/8805 , B29K2301/10
摘要： The present invention provides a method and apparatus for producing a crosslinked foamed article. Such a method comprises the steps of: (a) uniformly mixing at least one crosslinkable resin, at least one crosslinking agent, at least one foaming agent, and some additives into a resin composition; (b) extruding the resin composition through a die into an extrudate of a predetermined shape; and (c) heating the extrudate to a temperature sufficient to cause crosslinking and foaming of the crosslinkable resin while being driven by a driving device to move in the extruding direction, thereby obtaining a crosslinked foamed article. By means of the present invention, the resin extrudate can progress smoothly through the heater or the mold.
摘要翻译：本发明提供一种交联发泡制品的制造方法和装置。这种方法包括以下步骤：（a）将至少一种可交联树脂，至少一种交联剂，至少一种发泡剂和一些添加剂均匀混合到树脂组合物中; （b）将树脂组合物通过模具挤出成预定形状的挤出物; 和（c）将挤出物加热至足以使交联性树脂发生交联和发泡的温度，同时由驱动装置驱动，从而在挤出方向上移动，从而获得交联发泡制品。通过本发明，树脂挤出物可以顺利进入加热器或模具。

7. 发明授权

US5923951A Method of making a flip-chip bonded GaAs-based opto-electronic device 失效
标题翻译：制造倒装芯片接合GaAs基光电器件的方法
公开(公告)号：US5923951A
公开(公告)日：1999-07-13
申请号：US688131
申请日：1996-07-29
申请人： Keith Wayne Goossen , Jenn-Ming Kuo , Yu-Chi Wang
发明人： Keith Wayne Goossen , Jenn-Ming Kuo , Yu-Chi Wang
IPC分类号： H01L23/12 , H01L21/20 , H01L21/306 , H01L25/16 , H01L31/02 , H01L33/00
CPC分类号： H01L25/167 , H01L21/30612 , H01L21/02395 , H01L21/02461 , H01L21/02546 , H01L2924/0002
摘要： In a method of making a flip-chip bonded GaAs-based opto-electronic device, removal of the GaAs substrate is facilitated by provision of a lattice matched (Al.sub.x Ga.sub.1-x)InP etch stop layer, exemplarily a Ga.sub.0.51 In.sub.0.49 P layer, and use of an etchant that isotropically etches GaAs such that an essentially mirror-like etch stop layer surface results, and that preferably exhibits an etch rate ratio of at least 200:1 for GaAs and the etch stop layer, respectively. Use of the novel substrate removal method can substantially increase device yield, and facilitate manufacture of large device arrays, e.g., arrays of detector/modulator diodes flip-chip bonded to Si CMOS chips.
摘要翻译：在制造倒装芯片接合的GaAs基光电器件的方法中，通过提供晶格匹配（Al x Ga 1-x）InP蚀刻停止层，例如Ga 0.51 In 0.49P层，便于去除GaAs衬底，以及使用各向同性蚀刻GaAs的蚀刻剂，使得基本上形成镜像的蚀刻停止层表面，并且优选地分别对GaAs和蚀刻停止层表现出至少200:1的蚀刻速率比。使用新颖的基板去除方法可以显着提高器件产量，并且便于制造大型器件阵列，例如与Si CMOS芯片接合的检测器/调制器二极管阵列。

8. 发明授权

US09728026B2 Electric lock device and door including the same 有权
公开(公告)号：US09728026B2
公开(公告)日：2017-08-08
申请号：US14955263
申请日：2015-12-01
申请人： Yu-Chi Wang
发明人： Yu-Chi Wang
IPC分类号： G05B19/00 , G07C9/00
CPC分类号： G07C9/00563 , G06K9/00087 , G06K9/00288 , G07C9/00309 , G07C2009/00341 , G07C2009/0065
摘要： A door includes a door panel and an electric lock device including a solar energy module, a biometric verification module, a control module and an electric lock. The solar energy module converts solar energy into an electricity output. The biometric verification module receives a biometric input signal relative to a biometric feature, determines whether the biometric feature conforms with a set of pre-established data, and generates a conforming signal if the determination is affirmative. The control module receives the conforming signal to generate a control signal and an unlocking signal. The electric lock receives the control signal and the unlocking signal. The electric lock operates to unlock the door panel.

9. 发明授权

US09035519B2 Electrical energy and mechanical energy conversion apparatus for vehicles 有权
标题翻译：车用电能和机械能转换装置
公开(公告)号：US09035519B2
公开(公告)日：2015-05-19
申请号：US13371368
申请日：2012-02-10
申请人： Yu-Chi Wang , Ren-Nien Jia
发明人： Yu-Chi Wang , Ren-Nien Jia
IPC分类号： H02K23/60 , H02K47/00 , H02K7/10 , H02K7/12 , B60K6/12 , B60K6/48 , B60L11/14 , B60K6/26 , H02K16/02
CPC分类号： H02K7/12 , B60K6/12 , B60K6/48 , B60K2006/262 , B60L11/14 , B60L2220/52 , H02K16/025 , Y02T10/6208 , Y02T10/6221 , Y02T10/6282 , Y02T10/641 , Y02T10/70 , Y02T10/7077
摘要： An electrical apparatus is provided. The electrical apparatus includes a first rotation device; a second rotation device co-axially disposed with the first rotation device for electromagnetically matching with each other; and a brake device connected to the second rotation device to constrain the second rotation device from a rotation.
摘要翻译：提供一种电气设备。电气设备包括第一旋转装置; 与所述第一旋转装置同轴设置的用于彼此电磁匹配的第二旋转装置; 以及连接到所述第二旋转装置以将所述第二旋转装置从旋转约束的制动装置。

10. 发明授权

US07842591B2 Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices 有权
标题翻译：用于集成III-V化合物半导体器件的短栅极长度电极的制造方法
公开(公告)号：US07842591B2
公开(公告)日：2010-11-30
申请号：US12153206
申请日：2008-05-15
申请人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L21/28
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785 , Y10S438/949 , Y10S438/95
摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
摘要翻译：公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

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