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1. 发明申请

US20120163364A1 ANTENNA SYSTEM AND WIRELESS COMMUNICATION DEVICE EMPLOYING THE SAME 有权
标题翻译：使用其的天线系统和无线通信设备
公开(公告)号：US20120163364A1
公开(公告)日：2012-06-28
申请号：US13084658
申请日：2011-04-12
申请人： TSUNG-CHI TSAI , SZU-TSO LIN
发明人： TSUNG-CHI TSAI , SZU-TSO LIN
IPC分类号： H04B1/44 , H01Q3/24 , H04B7/216
CPC分类号： H04B1/3838 , H01Q1/243 , H01Q21/28
摘要： An antenna system in a wireless communication device includes a first antenna, a second antenna, a baseband microchip, a signal sensing unit, a logical circuit, and a switch unit. The first antenna receives and transmits wireless signals; the second antenna transmits wireless signals. The baseband microchip processes the wireless signals and provides a voltage logic signal. The logical circuit logically processes the voltage logic signal and the command signal to generate different switch signals, and the switch unit is controlled by the switch signals from the logical circuit to connect to the first antenna or to the second antenna to transmit the wireless signals.
摘要翻译：无线通信设备中的天线系统包括第一天线，第二天线，基带微芯片，信号感测单元，逻辑电路和开关单元。第一天线接收和发送无线信号; 第二天线发射无线信号。基带微芯片处理无线信号并提供电压逻辑信号。逻辑电路逻辑地处理电压逻辑信号和命令信号以产生不同的开关信号，并且开关单元由来自逻辑电路的开关信号控制以连接到第一天线或第二天线以发送无线信号。

2. 发明授权

US07842591B2 Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices 有权
标题翻译：用于集成III-V化合物半导体器件的短栅极长度电极的制造方法
公开(公告)号：US07842591B2
公开(公告)日：2010-11-30
申请号：US12153206
申请日：2008-05-15
申请人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L21/28
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785 , Y10S438/949 , Y10S438/95
摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
摘要翻译：公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

3. 发明申请

US20050149885A1 Rugged heterojunction bipolar transistor power device and the method thereof 审中-公开
标题翻译：坚固的异质结双极晶体管功率器件及其方法
公开(公告)号：US20050149885A1
公开(公告)日：2005-07-07
申请号：US10747051
申请日：2003-12-30
申请人： Yu-Chi Wang , Jen-Hao Huang , Tsung-Chi Tsai , Min-Chang Tu
发明人： Yu-Chi Wang , Jen-Hao Huang , Tsung-Chi Tsai , Min-Chang Tu
IPC分类号： G06F17/50 , H01L29/73 , H01L29/737
CPC分类号： H01L29/7371 , H01L29/7304
摘要： A rugged heterojunction bipolar transistor (HBT) power device and the optimal design method thereof are disclosed. By combining the epitaxial layer structure design (embedded emitter ballasting resistor and high breakdown voltage) and power cell design (clamping diodes and base ballasting resistor optimization), HBT power devices with excellent power performance and high ruggedness can be obtained.
摘要翻译：公开了一种坚固的异质结双极晶体管（HBT）功率器件及其最佳设计方法。通过组合外延层结构设计（嵌入式发射极镇流电阻和高击穿电压）和功率单元设计（钳位二极管和基极镇流电阻优化），可以获得具有出色的功率性能和高耐久性的HBT功率器件。

4. 发明授权

US08570900B2 Antenna system and wireless communication device employing the same 有权
标题翻译：天线系统和采用该天线系统的无线通信装置
公开(公告)号：US08570900B2
公开(公告)日：2013-10-29
申请号：US13084658
申请日：2011-04-12
申请人： Tsung-Chi Tsai , Szu-Tso Lin
发明人： Tsung-Chi Tsai , Szu-Tso Lin
IPC分类号： H04L12/28
CPC分类号： H04B1/3838 , H01Q1/243 , H01Q21/28
摘要： An antenna system in a wireless communication device includes a first antenna, a second antenna, a baseband microchip, a signal sensing unit, a logical circuit, and a switch unit. The first antenna receives and transmits wireless signals; the second antenna transmits wireless signals. The baseband microchip processes the wireless signals and provides a voltage logic signal. The logical circuit logically processes the voltage logic signal and the command signal to generate different switch signals, and the switch unit is controlled by the switch signals from the logical circuit to connect to the first antenna or to the second antenna to transmit the wireless signals.
摘要翻译：无线通信设备中的天线系统包括第一天线，第二天线，基带微芯片，信号感测单元，逻辑电路和开关单元。第一天线接收和发送无线信号; 第二天线发射无线信号。基带微芯片处理无线信号并提供电压逻辑信号。逻辑电路逻辑地处理电压逻辑信号和命令信号以产生不同的开关信号，并且开关单元由来自逻辑电路的开关信号控制以连接到第一天线或第二天线以发送无线信号。

5. 发明申请

US20080220599A1 Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices 有权
标题翻译：用于集成III-V化合物半导体器件的短栅极长度电极的制造方法
公开(公告)号：US20080220599A1
公开(公告)日：2008-09-11
申请号：US12153206
申请日：2008-05-15
申请人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Cheng-Kuo Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L21/28
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785 , Y10S438/949 , Y10S438/95
摘要： A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
摘要翻译：公开了一种用于集成的III-V化合物半导体器件的短栅极长度电极的方法，特别是用于公共衬底上的集成HBT / HEMT器件的方法。该方法基于双抗蚀剂工艺，其中使用第一薄的光致抗蚀剂层来限定栅极尺寸，而第二较厚的光致抗蚀剂层用于在表面上获得更好的覆盖以便于栅极金属提升 - 关闭与通过常规单抗蚀剂工艺制造的那些相比，双重抗蚀剂方法不仅降低了最终栅极长度，而且减小了栅极凹槽底切。此外，本发明的双电阻法也有利于制造栅极长度均匀性好的多栅极器件。

6. 发明申请

US20070278523A1 Structure and a method for monolithic integration of HBT, depletion-mode HEMT and enhancement-mode HEMT on the same substrate 审中-公开
标题翻译： HBT，耗尽型HEMT和增强型HEMT在同一衬底上单片集成的结构和方法
公开(公告)号：US20070278523A1
公开(公告)日：2007-12-06
申请号：US11446206
申请日：2006-06-05
申请人： Heng-Kuang Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
发明人： Heng-Kuang Lin , Chia-Liang Chao , Ming-Chang Tu , Tsung-Chi Tsai , Yu-Chi Wang
IPC分类号： H01L29/739
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/0605 , H01L29/66318 , H01L29/7371 , H01L29/7785
摘要： An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT as well as passive devices, that enabling monolithic integration of a significant number of devices on a common substrate by a cost-effective way.
摘要翻译：公开了一种外延层结构和用于在公共衬底上制造HBT和HEMT的方法。外延层通常在一组HEMT层的顶部上包括一组HBT层。该方法可用于制造HBT，E模式HEMT和D模式HEMT以及无源器件，可以通过成本有效的方式在大量基板上实现大量器件的单片集成。

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