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1. 发明授权

US5751913A Reconfigurable neural network and difference-square neuron 失效
标题翻译：可重构神经网络和差分平方神经元
公开(公告)号：US5751913A
公开(公告)日：1998-05-12
申请号：US688055
申请日：1996-07-29
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Fang-Ru Hsu , Wan-Yu Meng
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Fang-Ru Hsu , Wan-Yu Meng
IPC分类号： G06N3/063 , G06N3/08 , G06F15/18
CPC分类号： G06N3/082 , G06N3/063
摘要： A reconfigurable neural network includes several switches each having at least two conductive leads, data flow direction of the conductive leads is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. Several processing elements each having leads connected to the switches, where the processing elements and the switches are interconnected in one-dimension manner. The neural network of interconnected switches and processing elements has a bit-serial input and a bit-serial output. Each of the processing elements comprising: (a) a serial-in-parallel-out difference-square accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out difference-square accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.
摘要翻译：可重新配置的神经网络包括几个开关，每个开关具有至少两个导电引线，导电引线的数据流动方向被编程为选择一个导电引线作为输入开关引线，并选择另一个导电引线作为输出开关引线。几个处理元件各自具有连接到开关的引线，其中处理元件和开关以一维方式互连。互连开关和处理元件的神经网络具有位串行输入和位串行输出。每个处理元件包括：（a）串并行输出差分平方累加器，其具有耦合到互连开关之一并产生第一输出的第一输入; （b）激活功能，用于变换串并行输出差分平方累加器的第一输出并产生第二输出; 和（c）串并联移位寄存器，用于将激活功能的第二输出串联移动到互连开关之一。

2. 发明授权

US5799134A One dimensional systolic array architecture for neural network 失效
标题翻译：神经网络的一维收缩阵列架构
公开(公告)号：US5799134A
公开(公告)日：1998-08-25
申请号：US441128
申请日：1995-05-15
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang
IPC分类号： G06N3/063 , G06N3/10 , G06F15/18
CPC分类号： G06N3/10 , G06N3/063
摘要： A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.
摘要翻译：用于实现神经网络的电路包括由微处理器控制的处理元件的一维收缩阵列。一维心脏收缩阵列可以实现包括具有各种不同激活功能的神经元的加权和径向型网络。流水线处理和分区用于优化收缩阵列中的数据流。因此，本发明的电路可以以非常有效的方式实现各种神经网络。

3. 发明授权

US5742741A Reconfigurable neural network 失效
标题翻译：可重构神经网络
公开(公告)号：US5742741A
公开(公告)日：1998-04-21
申请号：US683254
申请日：1996-07-18
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Yeh-Rong Hsu , Huang-Lin Yang , Chung-Chih Chang
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Yeh-Rong Hsu , Huang-Lin Yang , Chung-Chih Chang
IPC分类号： G06N3/063 , G06N3/08 , G06F15/18
CPC分类号： G06N3/082 , G06N3/063
摘要： A reconfigurable neural network is disclosed. The neural network includes a plurality of switches each having at least two conductive leads, wherein data flow direction of the conductive leads of the switches is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. A plurality of processing elements each having a plurality of leads connected to the switches, wherein the processing elements and the switches are interconnected in one-dimension manner. Each of the processing elements comprising: (a) a serial-in-parallel-out accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.
摘要翻译：公开了一种可重构神经网络。神经网络包括多个开关，每个开关具有至少两个导电引线，其中开关的导电引线的数据流动方向被编程为选择一个导电引线作为输入开关引线，并选择另一个导电引线作为输出开关引线。多个处理元件各自具有连接到开关的多个引线，其中处理元件和开关以一维方式互连。每个处理元件包括：（a）串并行输出累加器，其具有耦合到互连开关中的一个并产生第一输出的第一输入; （b）激活功能，用于变换串并行输出累加器的第一输出并产生第二输出; 和（c）串并联移位寄存器，用于将激活功能的第二输出串联移动到互连开关之一。

4. 发明授权

US08305251B2 Wireless remote control system 有权
标题翻译：无线遥控系统
公开(公告)号：US08305251B2
公开(公告)日：2012-11-06
申请号：US12702792
申请日：2010-02-09
申请人： Tzi-Dar Chiueh
发明人： Tzi-Dar Chiueh
IPC分类号： H04L17/02
CPC分类号： G08C23/02
摘要： A wireless remote control system is provided. This system includes a remote controller, plural detectors, and a decision module. The detectors are used for detecting the frequency a wireless signal emitted by the remote controller and respectively generate a detecting result. Based on at least one frequency difference between the detecting results, the decision module determines how the remote controller is moving and thereby generates a control signal. Because the decision module needs no knowledge of the frequency of the emitted wireless signal, the wireless remote controller has the advantages of small size, low cost, and low power consumption.
摘要翻译：提供无线遥控系统。该系统包括遥控器，多个检测器和决定模块。检测器用于检测由遥控器发射的无线信号的频率，并分别产生检测结果。基于检测结果之间的至少一个频率差，决定模块确定遥控器如何移动，从而产生控制信号。由于决策模块不需要了解发射无线信号的频率，所以无线遥控器具有体积小，成本低，功耗低的优点。

5. 发明授权

US06674824B1 Method and circuitry for controlling a phase-locked loop by analog and digital signals 有权
标题翻译：用于通过模拟和数字信号控制锁相环的方法和电路
公开(公告)号：US06674824B1
公开(公告)日：2004-01-06
申请号：US09339704
申请日：1999-06-24
申请人： Tzi-Dar Chiueh , Jen-Shi Wu , Jin-Bin Yang
发明人： Tzi-Dar Chiueh , Jen-Shi Wu , Jin-Bin Yang
IPC分类号： H04D324
CPC分类号： H03L7/187 , H03K3/0322 , H03L7/089 , H03L7/0995 , H03L7/10 , H03L7/193
摘要： A mixed-signal-controlled phase-locked loop is provided. This loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, a phase-frequency detector circuit electrically connected to the mixed-signal-controlled oscillator circuit, detecting the phase and the oscillating frequency of the oscillating signal and comparing the phase and the oscillating frequency with those of a reference signal to generate an error signal after the phase and oscillating frequency are detected, and a mixed-control-signal-producing circuit electrically connected to the mixed-signal-controlled oscillator circuit and the phase-frequency detector circuit for receiving the error signal to output the analog control signal and the digital control signal to the mixed-signal-controlled oscillator circuit.
摘要翻译：提供了混合信号控制的锁相环。该回路包括混合信号控制振荡器电路，用于响应于数字控制信号和模拟控制信号产生具有振荡频率和相位的振荡信号，相位频率检测器电路电连接到混合信号 - 控制振荡电路，检测振荡信号的相位和振荡频率，并将相位和振荡频率与参考信号的相位和振荡频率进行比较，以在检测到相位和振荡频率之后产生误差信号，混合控制信号电连接到混合信号控制振荡器电路和相位频率检测器电路，用于接收误差信号，以将模拟控制信号和数字控制信号输出到混合信号控制振荡器电路。

6. 发明申请

US20170089609A1 Intelligent Ignition System of Water Heater 审中-公开
公开(公告)号：US20170089609A1
公开(公告)日：2017-03-30
申请号：US15059356
申请日：2016-03-03
申请人： Tzi-Dar Chiueh , Chun-Ming Huang , Chen-Chia Chen , Chien-Ming Wu
发明人： Tzi-Dar Chiueh , Chun-Ming Huang , Chen-Chia Chen , Chien-Ming Wu
IPC分类号： F24H9/20 , F23Q3/00
CPC分类号： F24H9/2035 , F23N2027/28 , F23N2031/02 , F23N2041/04 , F23Q3/008
摘要： The ignition system includes a mini hydroelectric generator module connecting an inlet pipe for generating electricity by water flow passing through the inlet pipe and it; a power quality monitoring module electrically connecting the mini hydroelectric generator module for monitoring output electricity quality of the mini hydroelectric generator module and switching on/off the electricity; an ignitor electrically connecting the power quality monitoring module for receiving electricity from the power quality monitoring module to ignite; and an electronic valve electrically connecting the power quality monitoring module for receiving electricity from the power quality monitoring module to switch on/off a gas pipe.

7. 发明授权

US07277479B2 Reconfigurable fir filter 有权
标题翻译：可重构冷杉过滤器
公开(公告)号：US07277479B2
公开(公告)日：2007-10-02
申请号：US10248920
申请日：2003-03-02
申请人： Tzi-Dar Chiueh , Kuan-Hung Chen
发明人： Tzi-Dar Chiueh , Kuan-Hung Chen
IPC分类号： H03K7/00 , G06F17/10
CPC分类号： H03H17/0294
摘要： A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.
摘要翻译：一系列数字处理单元（DPU）被连接以形成有限脉冲响应（FIR）滤波器。每个DPU包括寄存器，多路复用器和系数乘法器。寄存器存储并延迟要过滤的输入数字信号。多路复用器具有连接到输入节点和寄存器的输出的输入，多路复用器的输出用于连接到下一级DPU。系数乘法器连接到寄存器的输出，并将输入信号乘以系数或系数的一部分。一组DPU可以设置多路复用器，使得每个DPU的寄存器存储用于处理单个滤波器系数的输入信号的相同部分。提供加法器以对DPU的输出进行求和并输出滤波信号。 FIR滤波器的关键路径与系数数和精度无关。

8. 发明授权

US07170800B2 Low-power delay buffer circuit 有权
标题翻译：低功耗延迟缓冲电路
公开(公告)号：US07170800B2
公开(公告)日：2007-01-30
申请号：US11124999
申请日：2005-05-09
申请人： Tzi-Dar Chiueh , Po-Chun Hsieh
发明人： Tzi-Dar Chiueh , Po-Chun Hsieh
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G06F5/10 , G06F2205/104 , G11C7/22 , G11C8/04 , G11C19/00
摘要： A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.
摘要翻译：提供了一种低功率延迟缓冲电路，其利用环形计数器作为地址解码器和用于存储器的锁存器阵列。为了降低功耗，门控时钟驱动树被应用于环计数器寻址架构。此外，类似的门控驱动器树被应用于锁存器阵列的输入和输出端口。延迟缓冲电路不仅可以实现低于基于SRAM的延迟缓冲器的功耗，而且可以在高频下运行，并且占用比基于SRAM的延迟缓冲器更少的布局面积。

9. 发明授权

US07113970B2 Complex-valued multiplier-and-accumulator 有权
标题翻译：复值乘法器和累加器
公开(公告)号：US07113970B2
公开(公告)日：2006-09-26
申请号：US09908588
申请日：2001-07-20
申请人： Tzi-Dar Chiueh , Yuan-Hao Huang
发明人： Tzi-Dar Chiueh , Yuan-Hao Huang
IPC分类号： G06F7/52
CPC分类号： G06F7/5443 , G06F7/4806
摘要： The multi-mode Multiplier-And-Accumulator of the present invention is used with the double-precision Complex-Valued Multiplier-And Accumulator as a main configuration, and the different precisions and digital modes make it more flexible, compared to the traditional real number Multiplier-And-Accumulator. In addition, it does not have a data alignment problem which occurs in the traditional application of different precision Subword Parallel processors. This kind of Multiplier-And-Accumulator takes a double-precision Complex-Valued Multiplier-And- Accumulator as the main configuration, with four double-precision real-valued multipliers and several groups of accumulators to assist in different modes ofoperation. Each double-precision real- valued multiplier can be segmented into four single-precision multipliers, and then double-precision multiplier products are obtained by means of displacement addition. If two real numbers which are continuous in time sequence are taken as the real number input and imaginary number input for the original complex-valued multipliers, the accumulated products include not only the present output accumulated product summation but also the output accumulated product summation of the previous time and the next time.
摘要翻译：本发明的多模式乘法器和累加器作为主要配置与双精度复值乘法器和累加器一起使用，与传统实数相比，不同的精度和数字模式使其更加灵活乘数和累加器。另外，它不具有在不同精度子字并行处理器的传统应用中出现的数据对齐问题。这种乘法和累加器采用双精度复值乘法器和累加器作为主要配置，具有四个双精度实数乘法器和多组累加器，以协助不同的操作模式。每个双精度实数乘法器可以分为四个单精度乘法器，然后通过位移附加获得双精度乘法器乘积。如果以时间序列连续的两个实数作为原始复值乘数的实数输入和虚数输入，则累积乘积不仅包括当前输出累积乘积和，而且还包括输出累积乘积和以前的时间和下一次。

10. 发明授权

US08692550B2 Method and apparatus for acquiring magnetic resonance imaging signals 有权
标题翻译：用于获取磁共振成像信号的方法和装置
公开(公告)号：US08692550B2
公开(公告)日：2014-04-08
申请号：US13050715
申请日：2011-03-17
申请人： Jyh-Horng Chen , Tzi-Dar Chiueh , Edzer L. Wu
发明人： Jyh-Horng Chen , Tzi-Dar Chiueh , Edzer L. Wu
IPC分类号： G01R33/44 , G01R33/483
CPC分类号： G01R33/4835
摘要： A method for acquiring MRI signals includes: applying one or more than one RF pulse, which carries at least two frequency components, and a slice/slab selection gradient to a subject, so that at least two slices/slabs of the subject respectively corresponding to the at least two frequency components are excited simultaneously; applying a plurality of spatial encoding gradients; applying a plurality of separation gradients for separating the at least two slices/slabs; and applying at least one coherent refocusing gradient between the plurality of separation gradients.
摘要翻译：一种用于获取MRI信号的方法包括：将一个或多于一个的RF脉冲（其携带至少两个频率分量）和切片/平板选择梯度施加到对象，使得被摄体的至少两个切片/平板分别对应于同时激励至少两个频率分量; 应用多个空间编码梯度; 施加多个用于分离所述至少两个切片/平板的分离梯度; 以及在所述多个分离梯度之间施加至少一个相干重聚焦梯度。

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