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1. 发明授权

US6041322A Method and apparatus for processing data in a neural network 失效
标题翻译：用于在神经网络中处理数据的方法和装置
公开(公告)号：US6041322A
公开(公告)日：2000-03-21
申请号：US839818
申请日：1997-04-18
申请人： Wan-Yu Meng , Cheng-Kai Chang , Hwai-Tsu Chang , Fang-Ru Hsu , Ming-Rong Lee
发明人： Wan-Yu Meng , Cheng-Kai Chang , Hwai-Tsu Chang , Fang-Ru Hsu , Ming-Rong Lee
IPC分类号： G06N3/04 , G06N3/063 , G06E1/00 , G06E3/00
CPC分类号： G06N3/0481 , G06N3/063
摘要： A digital artificial neural network (ANN) reduces memory requirements by storing sample transfer function representing output values for multiple nodes. Each nodes receives an input value representing the information to be processed by the network. Additionally, the node determines threshold values indicative of boundaries for application of the sample transfer function for the node. From the input value received, the node generates an intermediate value. Based on the threshold values and the intermediate value, the node determines an output value in accordance with the sample transfer function.
摘要翻译：数字人工神经网络（ANN）通过存储表示多个节点的输出值的样本传递函数来减少存储器需求。每个节点接收表示网络要处理的信息的输入值。另外，节点确定指示用于节点的样本传递函数的应用边界的阈值。从接收的输入值中，节点生成中间值。基于阈值和中间值，节点根据样本传递函数确定输出值。

2. 发明授权

US5751913A Reconfigurable neural network and difference-square neuron 失效
标题翻译：可重构神经网络和差分平方神经元
公开(公告)号：US5751913A
公开(公告)日：1998-05-12
申请号：US688055
申请日：1996-07-29
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Fang-Ru Hsu , Wan-Yu Meng
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Fang-Ru Hsu , Wan-Yu Meng
IPC分类号： G06N3/063 , G06N3/08 , G06F15/18
CPC分类号： G06N3/082 , G06N3/063
摘要： A reconfigurable neural network includes several switches each having at least two conductive leads, data flow direction of the conductive leads is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. Several processing elements each having leads connected to the switches, where the processing elements and the switches are interconnected in one-dimension manner. The neural network of interconnected switches and processing elements has a bit-serial input and a bit-serial output. Each of the processing elements comprising: (a) a serial-in-parallel-out difference-square accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out difference-square accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.
摘要翻译：可重新配置的神经网络包括几个开关，每个开关具有至少两个导电引线，导电引线的数据流动方向被编程为选择一个导电引线作为输入开关引线，并选择另一个导电引线作为输出开关引线。几个处理元件各自具有连接到开关的引线，其中处理元件和开关以一维方式互连。互连开关和处理元件的神经网络具有位串行输入和位串行输出。每个处理元件包括：（a）串并行输出差分平方累加器，其具有耦合到互连开关之一并产生第一输出的第一输入; （b）激活功能，用于变换串并行输出差分平方累加器的第一输出并产生第二输出; 和（c）串并联移位寄存器，用于将激活功能的第二输出串联移动到互连开关之一。

3. 发明授权

US06408269B1 Frame-based subband Kalman filtering method and apparatus for speech enhancement 有权
标题翻译：基于帧的子带卡尔曼滤波方法和语音增强装置
公开(公告)号：US06408269B1
公开(公告)日：2002-06-18
申请号：US09261396
申请日：1999-03-03
申请人： Wen-Rong Wu , Po-Cheng Chen , Hwai-Tsu Chang , Chun-Hung Kuo
发明人： Wen-Rong Wu , Po-Cheng Chen , Hwai-Tsu Chang , Chun-Hung Kuo
IPC分类号： G10L2102
CPC分类号： G10L21/0208 , G10L21/0232 , G10L25/18
摘要： A method and apparatus for enhancing a speech signal contaminated by additive noise through Kalman filtering. The speech is decomposed into subband speech signals by a multichannel analysis filter bank including bandpass filters and decimation filters. Each subband speech signal is converted into a sequence of voice frames. A plurality of low-order Kalman filters are respectively applied to filter each of the subband speech signals. The autoregression (AR) parameters which are required for each Kalman filter are estimated frame-by-frame by using a correlation subtraction method to estimate the autocorrelation function and solving the corresponding Yule-Walker equations for each of the subband speech signals, respectively. The filtered subband speech signals are then combined or synthesized by a multichannel synthesis filter bank including interpolation filters and bandpass filters, and the outputs of the multichannel synthesis filter bank are summed in an adder to produce the enhanced fullband speech signal.
摘要翻译：一种用于通过卡尔曼滤波增强被加性噪声污染的语音信号的方法和装置。通过包括带通滤波器和抽取滤波器的多通道分析滤波器组将语音分解成子带语音信号。每个子带语音信号被转换成一系列语音帧。分别应用多个低阶卡尔曼滤波器来滤波每个子带语音信号。通过使用相关减法来估计每个卡尔曼滤波器所需的自回归（AR）参数，以分别估计每个子带语音信号的自相关函数和求解相应的Yule-Walker方程。滤波后的子带语音信号然后由包括内插滤波器和带通滤波器的多通道合成滤波器组合或合成，并且多路合成滤波器组的输出在加法器中相加以产生增强的全频带语音信号。

4. 发明授权

US6052658A Method of amplitude coding for low bit rate sinusoidal transform vocoder 失效
标题翻译：低比特率正弦变换声码器的幅度编码方法
公开(公告)号：US6052658A
公开(公告)日：2000-04-18
申请号：US94448
申请日：1998-06-10
申请人： De-Yu Wang , Wen-Whei Chang , Hwai-Tsu Chang , Huang-Lin Yang
发明人： De-Yu Wang , Wen-Whei Chang , Hwai-Tsu Chang , Huang-Lin Yang
IPC分类号： G10L19/02
CPC分类号： G10L19/02
摘要： The present invention provides a sinusoidal transform vocoder based on the Bark spectrum, which has high quality and low bit rate for coding. The present invention includes the steps of transforming a harmonic sine wave from a frequency spectrum to a perception-based Bark spectrum. An equal-loudness pre-emphasis and the loudness to a subjective loudness transformation are also involved in the method. Last, a pulse code modulation (PCM) is used to quantize the subjective loudness to obtain quantized subjective loudness. In synthesis, the Bark spectrum is inversely processed to obtain the excitation pattern following the sone-to-phone conversion and equal-loudness deemphasis. Then, the sine wave amplitudes can be estimated from the excitation pattern by assuming that the amplitudes belonging to the same critical band are equal.
摘要翻译：本发明提供一种基于Bark频谱的正弦变换声码器，其具有高质量和低码率的编码。本发明包括将谐波正弦波从频谱变换为基于感知的树皮光谱的步骤。该方法中也涉及到等响度预加重和主观响度变换的响度。最后，使用脉冲编码调制（PCM）来量化主观响度以获得量化的主观响度。在合成中，Bark频谱被反向处理，以获得在单声道到电话转换和等响度去加重之后的激励模式。然后，可以通过假设属于相同临界频带的振幅相等，从激励模式估计正弦波幅度。

5. 发明授权

US5742741A Reconfigurable neural network 失效
标题翻译：可重构神经网络
公开(公告)号：US5742741A
公开(公告)日：1998-04-21
申请号：US683254
申请日：1996-07-18
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Yeh-Rong Hsu , Huang-Lin Yang , Chung-Chih Chang
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang , Yeh-Rong Hsu , Huang-Lin Yang , Chung-Chih Chang
IPC分类号： G06N3/063 , G06N3/08 , G06F15/18
CPC分类号： G06N3/082 , G06N3/063
摘要： A reconfigurable neural network is disclosed. The neural network includes a plurality of switches each having at least two conductive leads, wherein data flow direction of the conductive leads of the switches is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. A plurality of processing elements each having a plurality of leads connected to the switches, wherein the processing elements and the switches are interconnected in one-dimension manner. Each of the processing elements comprising: (a) a serial-in-parallel-out accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.
摘要翻译：公开了一种可重构神经网络。神经网络包括多个开关，每个开关具有至少两个导电引线，其中开关的导电引线的数据流动方向被编程为选择一个导电引线作为输入开关引线，并选择另一个导电引线作为输出开关引线。多个处理元件各自具有连接到开关的多个引线，其中处理元件和开关以一维方式互连。每个处理元件包括：（a）串并行输出累加器，其具有耦合到互连开关中的一个并产生第一输出的第一输入; （b）激活功能，用于变换串并行输出累加器的第一输出并产生第二输出; 和（c）串并联移位寄存器，用于将激活功能的第二输出串联移动到互连开关之一。

6. 发明授权

US5581496A Zero-flag generator for adder 失效
标题翻译：零标志发生器用于加法器
公开(公告)号：US5581496A
公开(公告)日：1996-12-03
申请号：US320236
申请日：1994-10-11
申请人： Shiang-Jhy Lai , Hwai-Tsu Chang
发明人： Shiang-Jhy Lai , Hwai-Tsu Chang
IPC分类号： G06F7/02 , G06F7/50 , G06F7/505 , G06F7/00
CPC分类号： G06F7/505 , G06F7/02 , G06F7/49905
摘要： Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.
摘要翻译：并行处理架构用于加法器及其“先行”零标志发生器，其产生加法器之和的最高有效位的标志信号。使用组合逻辑电路产生先行零标志，组合逻辑电路从加法器的不同位的加法和加法器馈送，然后解码。组合逻辑电路可以包括门阵列中的与门和异或门，并且解码器可以是可编程逻辑阵列（PLA）。这样生成的零标志的计算时间比加法器的和的计算时间短。

7. 发明授权

US5799134A One dimensional systolic array architecture for neural network 失效
标题翻译：神经网络的一维收缩阵列架构
公开(公告)号：US5799134A
公开(公告)日：1998-08-25
申请号：US441128
申请日：1995-05-15
申请人： Tzi-Dar Chiueh , Hwai-Tsu Chang
发明人： Tzi-Dar Chiueh , Hwai-Tsu Chang
IPC分类号： G06N3/063 , G06N3/10 , G06F15/18
CPC分类号： G06N3/10 , G06N3/063
摘要： A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.
摘要翻译：用于实现神经网络的电路包括由微处理器控制的处理元件的一维收缩阵列。一维心脏收缩阵列可以实现包括具有各种不同激活功能的神经元的加权和径向型网络。流水线处理和分区用于优化收缩阵列中的数据流。因此，本发明的电路可以以非常有效的方式实现各种神经网络。

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