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1. 发明申请

US20100127739A1 SPREAD SPECTRUM CONTROL PLL CIRCUIT AND ITS START-UP METHOD 有权
标题翻译：传播频谱控制PLL电路及其启动方法
公开(公告)号：US20100127739A1
公开(公告)日：2010-05-27
申请号：US12595008
申请日：2008-03-18
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
IPC分类号： H03L7/08
CPC分类号： H03L7/197 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976
摘要： A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).
摘要翻译：校准电路（19）调整环路滤波器电路（13）中的电荷泵电路（12）的充电电流和滤波电容器的电容值中的至少一个以及压控振荡器（14）的增益中的至少一个），取决于输入到校准电路（10）的参考时钟信号的频率。

2. 发明授权

US07986175B2 Spread spectrum control PLL circuit and its start-up method 有权
标题翻译：扩频控制PLL电路及其启动方式
公开(公告)号：US07986175B2
公开(公告)日：2011-07-26
申请号：US12595008
申请日：2008-03-18
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Michiyo Yamamoto
IPC分类号： H03L7/06
CPC分类号： H03L7/197 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976
摘要： A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).
摘要翻译：校准电路（19）调整环路滤波器电路（13）中的电荷泵电路（12）的充电电流和滤波电容器的电容值中的至少一个以及压控振荡器（14）的增益中的至少一个），取决于输入到校准电路（10）的参考时钟信号的频率。

3. 发明申请

US20100214031A1 SPECTRUM SPREAD CLOCK GENERATION DEVICE 有权
标题翻译：频谱扩展时钟发生装置
公开(公告)号：US20100214031A1
公开(公告)日：2010-08-26
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03L7/06 , H03J7/04 , H03L7/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

4. 发明授权

US08085101B2 Spread spectrum clock generation device 有权
标题翻译：扩频时钟生成装置
公开(公告)号：US08085101B2
公开(公告)日：2011-12-27
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03B29/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

5. 发明申请

US20100013692A1 A/D CONVERTER 有权
标题翻译： A / D转换器
公开(公告)号：US20100013692A1
公开(公告)日：2010-01-21
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/34
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock.A clock generator circuit (104) for automatically generating an operation clock is provided inside an A/D converter (100) to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器（100）内部设置用于自动生成操作时钟的时钟发生器电路（104），使得A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

6. 发明授权

US06512414B2 Automatic filter tuning control system 有权
公开(公告)号：US06512414B2
公开(公告)日：2003-01-28
申请号：US09901603
申请日：2001-07-11
申请人： Akio Yokoyama , Hisashi Takahashi , Michiyo Yamamoto , Norihide Kinugasa , Mamoru Arayashiki
发明人： Akio Yokoyama , Hisashi Takahashi , Michiyo Yamamoto , Norihide Kinugasa , Mamoru Arayashiki
IPC分类号： H03K500
CPC分类号： H03H11/0433
摘要： To tune the center frequency of a gm-C filter, which is a bandpass filter with a narrow bandwidth, to a target frequency, only while the filter is being tuned, the original circuit configuration of the filter is replaced with an alternative configuration that realizes a high signal-to-noise ratio. A characteristic tuner generates and inputs an impulse signal, pulse signal or step signal to the filter being tuned and thereby detects and adjusts the center frequency of the filter. And the tuning result is stored on a nonvolatile memory for future reuse. When the filter is operated, the characteristic tuner stops operating to cut down the power dissipation.

7. 发明授权

US08582708B2 Clock and data recovery circuit 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US08582708B2
公开(公告)日：2013-11-12
申请号：US13344201
申请日：2012-01-05
申请人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
发明人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/0996
摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
摘要翻译：时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

8. 发明授权

US07986256B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07986256B2
公开(公告)日：2011-07-26
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路，使A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

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