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    • 1. 发明申请
    • A/D CONVERTER
    • A / D转换器
    • US20100013692A1
    • 2010-01-21
    • US12377989
    • 2007-08-10
    • Michiyo YamamotoKenji MurataMasakazu Shigemori
    • Michiyo YamamotoKenji MurataMasakazu Shigemori
    • H03M1/34
    • H03M1/1245H03M1/365
    • An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock.A clock generator circuit (104) for automatically generating an operation clock is provided inside an A/D converter (100) to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
    • 操作常规A / D转换器需要外部输入操作时钟信号,并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。 在A / D转换器(100)内部设置用于自动生成操作时钟的时钟发生器电路(104),使得A / D转换器不需要外部输入操作时钟。 此外,提供用于检测A / D转换器的组成部分的操作时间的电路,以产生A / D转换器被最佳操作的时钟,从而实现高速操作和低功耗。
    • 2. 发明申请
    • CLOCK AND DATA RECOVERY CIRCUIT
    • 时钟和数据恢复电路
    • US20120105115A1
    • 2012-05-03
    • US13344201
    • 2012-01-05
    • Michiyo YAMAMOTOKenji MurataKazuya Hatooka
    • Michiyo YAMAMOTOKenji MurataKazuya Hatooka
    • H03L7/06
    • H04L7/0337H03L7/091H03L7/0996
    • A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
    • 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路,采样电路,对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样,并产生多个 数据信号,数据恢复单元,其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元,存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。
    • 6. 发明授权
    • Clock and data recovery circuit
    • 时钟和数据恢复电路
    • US08582708B2
    • 2013-11-12
    • US13344201
    • 2012-01-05
    • Michiyo YamamotoKenji MurataKazuya Hatooka
    • Michiyo YamamotoKenji MurataKazuya Hatooka
    • H04L7/00
    • H04L7/0337H03L7/091H03L7/0996
    • A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
    • 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路,采样电路,对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样,并产生多个 数据信号,数据恢复单元,其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元,存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。
    • 8. 发明授权
    • A/D converter
    • A / D转换器
    • US07986256B2
    • 2011-07-26
    • US12377989
    • 2007-08-10
    • Michiyo YamamotoKenji MurataMasakazu Shigemori
    • Michiyo YamamotoKenji MurataMasakazu Shigemori
    • H03M1/12
    • H03M1/1245H03M1/365
    • An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
    • 操作常规A / D转换器需要外部输入操作时钟信号,并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。 在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路,使A / D转换器不需要外部输入操作时钟。 此外,提供用于检测A / D转换器的组成部分的操作时间的电路,以产生A / D转换器被最佳操作的时钟,从而实现高速操作和低功耗。