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1. 发明申请

US20100013692A1 A/D CONVERTER 有权
标题翻译： A / D转换器
公开(公告)号：US20100013692A1
公开(公告)日：2010-01-21
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/34
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock.A clock generator circuit (104) for automatically generating an operation clock is provided inside an A/D converter (100) to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器（100）内部设置用于自动生成操作时钟的时钟发生器电路（104），使得A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

2. 发明授权

US07986256B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07986256B2
公开(公告)日：2011-07-26
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路，使A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

3. 发明申请

US20100007541A1 A/D CONVERTER 失效
标题翻译： A / D转换器
公开(公告)号：US20100007541A1
公开(公告)日：2010-01-14
申请号：US12439444
申请日：2007-08-10
申请人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
发明人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
IPC分类号： H03M1/34
CPC分类号： H03M1/0624 , H03M1/206 , H03M1/365
摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
摘要翻译：传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

4. 发明授权

US07834794B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07834794B2
公开(公告)日：2010-11-16
申请号：US12439444
申请日：2007-08-10
申请人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
发明人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , H03M1/206 , H03M1/365
摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
摘要翻译：传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

5. 发明申请

US20100214031A1 SPECTRUM SPREAD CLOCK GENERATION DEVICE 有权
标题翻译：频谱扩展时钟发生装置
公开(公告)号：US20100214031A1
公开(公告)日：2010-08-26
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03L7/06 , H03J7/04 , H03L7/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

6. 发明申请

US20120105115A1 CLOCK AND DATA RECOVERY CIRCUIT 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US20120105115A1
公开(公告)日：2012-05-03
申请号：US13344201
申请日：2012-01-05
申请人： Michiyo YAMAMOTO , Kenji Murata , Kazuya Hatooka
发明人： Michiyo YAMAMOTO , Kenji Murata , Kazuya Hatooka
IPC分类号： H03L7/06
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/0996
摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
摘要翻译：时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

7. 发明授权

US08582708B2 Clock and data recovery circuit 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US08582708B2
公开(公告)日：2013-11-12
申请号：US13344201
申请日：2012-01-05
申请人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
发明人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/0996
摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
摘要翻译：时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

8. 发明授权

US08085101B2 Spread spectrum clock generation device 有权
标题翻译：扩频时钟生成装置
公开(公告)号：US08085101B2
公开(公告)日：2011-12-27
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03B29/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

9. 外观设计

USD599785S1 Earphone 有权
公开(公告)号：USD599785S1
公开(公告)日：2009-09-08
申请号：US29296666
申请日：2007-10-25
申请人： Takeshi Matsuda , Kenji Hatano , Masaji Komuro , Kenji Murata
设计人： Takeshi Matsuda , Kenji Hatano , Masaji Komuro , Kenji Murata

10. 发明授权

US06917856B2 Robot 有权
标题翻译：机器人
公开(公告)号：US06917856B2
公开(公告)日：2005-07-12
申请号：US10343913
申请日：2002-04-12
申请人： Kenji Murata
发明人： Kenji Murata
IPC分类号： B25J9/16 , B25J9/18 , B25J19/00 , G05B19/04 , G05B19/18
CPC分类号： B25J9/1674 , G05B2219/40218
摘要： It is constructed so as to detect a joint movement position of a robot arm by a position detector and a joint movement speed is calculated from change amounts of the joint movement position and elapsed time and is compared with an allowable movement speed and unlocking and locking of a brake are controlled so that the joint movement speed of an arm at the time of brake unlocking becomes within a constant value even when a shape, an attitude and a load condition of the robot arm vary. Therefore, movement work of the arm by the brake unlocking can be performed alone and a robot with high safety can be obtained.
摘要翻译：其结构是通过位置检测器检测机器人手臂的关节运动位置，并且根据关节运动位置和经过时间的变化量计算关节运动速度，并将其与允许的运动速度进行比较并解锁和锁定控制制动器，使得即使当机器人手臂的形状，姿态和负载条件变化时，制动器解锁时的臂的关节移动速度也变为恒定值。因此，可以单独执行通过制动器解锁的臂的移动工作，并且可以获得具有高安全性的机器人。

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