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1. 发明授权

US5258631A Semiconductor device having a two-dimensional electron gas as an active layer 失效
标题翻译：具有二维电子气体作为活性层的半导体装置
公开(公告)号：US5258631A
公开(公告)日：1993-11-02
申请号：US884878
申请日：1992-05-18
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/06 , H01L29/167 , H01L29/30 , H01L31/072
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用其源极和漏极区域的形成来制造通过引入杂质例如通过离子注入引起异质结的紊乱的技术或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

2. 发明授权

US5381027A Semiconductor device having a heterojunction and a two dimensional gas as an active layer 失效
标题翻译：具有异质结和二维气体作为有源层的半导体器件
公开(公告)号：US5381027A
公开(公告)日：1995-01-10
申请号：US134622
申请日：1993-10-12
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/804 , H01L29/784
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

3. 发明授权

US4914488A Compound semiconductor structure and process for making same 失效
标题翻译：复合半导体结构及其制造方法
公开(公告)号：US4914488A
公开(公告)日：1990-04-03
申请号：US189179
申请日：1988-05-02
申请人： Masao Yamane , Tomoyoshi Mishima , Shigeo Goto , Susumu Takahashi , Makoto Morioka
发明人： Masao Yamane , Tomoyoshi Mishima , Shigeo Goto , Susumu Takahashi , Makoto Morioka
IPC分类号： H01L21/22 , H01L21/335 , H01L29/15 , H01L29/778
CPC分类号： H01L29/66462 , H01L21/22 , H01L29/155 , H01L29/7783 , H01L29/7787
摘要： A compound semiconductor structure in the form of a superlattice film with effectively graded average composition, comprising an alternating lamination of two kinds of layers of different composition to form pairs of layers, the ratio of the thickness of one layer to the thickness of the other in said pairs of layers being gradually varied in the direction of thickness throughout successive pairs, thereby the average composition being effectively graded throughout the pairs. In a hetero-junction field effect transistor, the layer of effectively graded composition is used between a semiconductor layer making low resistance contact with a current-supplying electrode and a semiconductor layer where a two dimensional channel is to be formed. In case of AlGaAs/GaAs system, the Al composition is varied. When the superlattice film is heat-treated, Al in the AlGaAs layer diffuses into the GaAs layer, yielding a film with actually smoothly graded Al mole fraction.
摘要翻译：具有有效分级平均组成的超晶格膜形式的化合物半导体结构，包括两种不同组成的层的交替叠层以形成一对层，一层的厚度与另一层的厚度之比所述成对的层在整个连续的对中在厚度方向上逐渐变化，从而平均组成在整个对中有效地分级。在异质结场效应晶体管中，在与供电电极进行低电阻接触的半导体层与要形成二维沟道的半导体层之间使用有效梯度组成的层。在AlGaAs / GaAs系统的情况下，Al组成是变化的。当超晶格膜被热处理时，AlGaAs层中的Al扩散到GaAs层中，产生具有平滑分级的Al摩尔分数的膜。

4. 发明申请

US20060157825A1 Semiconductor device and manufacturing the same 审中-公开
标题翻译：半导体器件和制造相同
公开(公告)号：US20060157825A1
公开(公告)日：2006-07-20
申请号：US11376116
申请日：2006-03-16
申请人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
发明人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
IPC分类号： H01L27/082
CPC分类号： H01L27/0825 , H01L27/0259 , H01L29/7371 , H01L2224/48091 , H01L2224/73265 , H03K17/08146 , H03K17/615 , H01L2924/00014
摘要： The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.
摘要翻译：本发明旨在提高对半导体器件的破坏性。具有连接在高输出的放大电路的输出（集电极和发射极）之间的达林顿的多个双极晶体管的保护电路与放大电路并联电连接。放大电路具有彼此并联连接的多个单元HBT（异质结双极晶体管）。保护电路具有包括具有多个双极型晶体管Q 1至Q 5的第一组保护电路和具有多个双极晶体管的第二组保护电路的两级配置。

5. 发明授权

US07045877B2 Semiconductor protection device 失效
标题翻译：半导体保护装置
公开(公告)号：US07045877B2
公开(公告)日：2006-05-16
申请号：US10420740
申请日：2003-04-23
申请人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
发明人： Yasunari Umemoto , Hideyuki Ono , Tomonori Tanoue , Yasuo Ohsone , Isao Ohbu , Chushiro Kusano , Atsushi Kurokawa , Masao Yamane
IPC分类号： H01L31/072
CPC分类号： H01L27/0825 , H01L27/0259 , H01L29/7371 , H01L2224/48091 , H01L2224/73265 , H03K17/08146 , H03K17/615 , H01L2924/00014
摘要： The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.
摘要翻译：本发明旨在提高对半导体器件的破坏性。具有连接在高输出的放大电路的输出（集电极和发射极）之间的达林顿的多个双极晶体管的保护电路与放大电路并联电连接。放大电路具有彼此并联连接的多个单元HBT（异质结双极晶体管）。保护电路具有包括具有多个双极型晶体管Q 1至Q 5的第一组保护电路和具有多个双极晶体管的第二组保护电路的两级配置。

6. 发明申请

US20070257332A1 BIPOLAR TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20070257332A1
公开(公告)日：2007-11-08
申请号：US11775716
申请日：2007-07-10
申请人： Atsushi KUROKAWA , Masao Yamane , Yoshinori Imamura
发明人： Atsushi KUROKAWA , Masao Yamane , Yoshinori Imamura
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/66318
摘要： A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film for masking thereby to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront, and the increase of resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.
摘要翻译：具有增强特性的双极晶体管通过蚀刻形成在发射极台面（上部发射极层）和基底电极下方的基底台面而制成，以在其大致矩形区域的边缘上具有突起区域。形成掩模膜例如绝缘膜以覆盖矩形区域和突起区域，并且通过使用用于掩蔽的绝缘膜来蚀刻基底层，从而形成基底台面。因此，可以防止沿着基极和发射极台面所面对的区域的边缘上的基极和发射极台面发生异常蚀刻，并且可以防止基极层和发射极层之间的电阻的增加，由此双极晶体管可以具有增强的特性。

7. 发明授权

US07256433B2 Bipolar transistor and a method of manufacturing the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07256433B2
公开(公告)日：2007-08-14
申请号：US10833142
申请日：2004-04-28
申请人： Atsushi Kurokawa , Masao Yamane , Yoshinori Imamura
发明人： Atsushi Kurokawa , Masao Yamane , Yoshinori Imamura
IPC分类号： H01L29/739
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/66318
摘要： A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.
摘要翻译：具有增强特性的双极晶体管通过蚀刻形成在发射极台面（上部发射极层）和基底电极下方的基底台面而制成，以便在其大致矩形区域的边缘上具有突起区域。形成掩模膜例如绝缘膜以覆盖矩形区域和突起区域，并且通过使用绝缘膜作为掩模蚀刻基底层以形成基底台面。因此，可以防止在基极和发射极台面彼此面对的区域的边缘上的基极和发射极台面发生异常蚀刻，并且可以防止基极层和发射极层之间的电阻的增加。由此双极晶体管可以具有增强的特性。

8. 发明授权

US07439622B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07439622B2
公开(公告)日：2008-10-21
申请号：US11581587
申请日：2006-10-17
申请人： Hitoshi Akamine , Masashi Suzuki , Masao Yamane , Tetsuaki Adachi
发明人： Hitoshi Akamine , Masashi Suzuki , Masao Yamane , Tetsuaki Adachi
IPC分类号： H01L23/48 , H01L23/52 , H01R11/00
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/16 , H01L27/088 , H01L29/0696 , H01L29/1083 , H01L29/4175 , H01L29/41758 , H01L29/4238 , H01L29/7835 , H01L2223/6644 , H01L2223/6688 , H01L2224/05599 , H01L2224/45099 , H01L2224/49111 , H01L2224/85399 , H01L2924/00014 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H03F3/189 , H03F3/211 , H03F3/601 , H03F3/68 , H03F3/72 , H03F2200/294 , H03F2200/372 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode terminals constitute a second transistor portion. The semiconductor device is quadrangular.
摘要翻译：本发明提供一种半导体器件，包括半导体衬底和形成在半导体衬底上的晶体管，其中构成晶体管的外部电极端子的控制电极端子和传输输出信号的第一电极端子设置在半导体的主表面上基板，其中控制电极端子设置为至少一个，并且多个第一电极端子布置在一侧，并且多个第一电极端子布置在另一侧，其中控制电极端子插入其间，其中包括控制电极端子和位于控制电极端子一侧的多个第一电极端子的部分构成第一晶体管部分，并且其中包括控制电极端子和位于第一晶体管部分上的多个第一电极端子的部分另一边的控制电极端子构成第二晶体管部分。半导体器件是四边形。

9. 发明申请

US20050156756A1 Vehicular communications apparatus and method 有权
标题翻译：车载通信装置及方法
公开(公告)号：US20050156756A1
公开(公告)日：2005-07-21
申请号：US11030290
申请日：2005-01-07
申请人： Susumu Fujita , Toru Takagi , Masao Yamane , Toshiro Muramatsu , Okihiko Nakayama
发明人： Susumu Fujita , Toru Takagi , Masao Yamane , Toshiro Muramatsu , Okihiko Nakayama
IPC分类号： G08G1/09 , G08G1/123 , G08G1/16 , H04B7/26 , G08G1/00
CPC分类号： G08G1/123
摘要： A vehicular communications apparatus is configured to calculate information on relative positions, relative velocities, and relative moving directions between own vehicle and other vehicles at a point such as a junction where other vehicles tend to affect running of the own vehicle, and to search for and decide other vehicles which are to be opponents of radio communications, based on a calculated result, and communication opponents are decided from among the searched other vehicles, and radio communications are conducted therewith, and then, the vehicular communications apparatus obtains information on the other vehicles, in a time-sequential manner and by radio communications, and present the information to a driver of the own vehicle from time to time, thereby causing the driver to recognize dynamic information on the other vehicles, enabling the own vehicle to smoothly join a flow of traffic at a junction, for example.
摘要翻译：车辆通信装置被配置为在其他车辆倾向于影响本车辆的行驶的点处，计算本车辆与其他车辆之间的相对位置，相对速度和相对移动方向的信息，并且搜索和根据计算结果，决定其他作为无线电通信对手的车辆，并从所搜索到的其他车辆中确定通信对手，并进行无线电通信，然后，车辆通信装置获取关于其他车辆的信息以时间顺序的方式和通过无线电通信，不时地将信息呈现给本车辆的驾驶员，从而使驾驶员识别其他车辆上的动态信息，使得本车能够平稳地加入流例如在交汇处的交通。

10. 发明申请

US20050116253A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050116253A1
公开(公告)日：2005-06-02
申请号：US10989388
申请日：2004-11-17
申请人： Masao Yamane , Atsushi Kurokawa , Shinya Osakabe , Eigo Tange , Yasushi Shigeno , Hiroyuki Takazawa
发明人： Masao Yamane , Atsushi Kurokawa , Shinya Osakabe , Eigo Tange , Yasushi Shigeno , Hiroyuki Takazawa
IPC分类号： H01L21/338 , H01L21/8252 , H01L27/06 , H01L29/778 , H01L29/812 , H01L29/739
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605
摘要： The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 17 is formed in an active region defined by an element separation portion 9 on a main surface of a substrate 1 comprising GaAs. The gate electrode 17 is patterned so as to extend in the vertical direction of the page surface between source electrodes 13 and drain electrodes 14, and to extend in left and right directions at other portions. Thus, the ratio of the gate electrode 17 disposed outside the active region is reduced, and the area of a gate pad 17A is reduced.
摘要翻译：本发明将用作射频模块中的开关元件的HEMT元件小型化。单个栅极电极17形成在由包含GaAs的基板1的主表面上的元件分离部分9限定的有源区域中。栅电极17被图案化以在源电极13和漏电极14之间的页表面的垂直方向上延伸，并且在其它部分沿左右方向延伸。因此，设置在有源区域之外的栅电极17的比率减小，并且栅极焊盘17A的面积减小。

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