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1. 发明申请

US20080160750A1 METHOD OF MANFACTURING SEMICONCUDTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080160750A1
公开(公告)日：2008-07-03
申请号：US11953127
申请日：2007-12-10
申请人： Toshiyuki TAKEWAKI , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takahara Kunugi
发明人： Toshiyuki TAKEWAKI , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takahara Kunugi
IPC分类号： H01L21/302 , H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

2. 发明授权

US08329584B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08329584B2
公开(公告)日：2012-12-11
申请号：US13151867
申请日：2011-06-02
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

3. 发明授权

US07955980B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07955980B2
公开(公告)日：2011-06-07
申请号：US12543128
申请日：2009-08-18
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

4. 发明授权

US07601640B2 Method of manfacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07601640B2
公开(公告)日：2009-10-13
申请号：US11953127
申请日：2007-12-10
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

5. 发明授权

US07629656B2 Semiconductor device guard ring 有权
标题翻译：半导体器件保护环
公开(公告)号：US07629656B2
公开(公告)日：2009-12-08
申请号：US11485438
申请日：2006-07-13
申请人： Mieko Hasegawa , Yasutaka Nakashiba
发明人： Mieko Hasegawa , Yasutaka Nakashiba
IPC分类号： H01L27/088
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring). The insulating interlayer group 20 is formed on the semiconductor substrate 10. The insulating interlayer group 30 is formed on the insulating interlayer group 20. The insulating interlayer group 30 is formed by an insulating material having a lower dielectric constant than that of the insulating interlayer group 20. The seal ring 40 is provided so as to surround the circuit forming regions D11 and D12. The seal ring 40 penetrates through the interface between the insulating interlayer group 20 and the insulating interlayer group 30 and is provided apart from the semiconductor substrate 10.
摘要翻译：半导体器件1包括半导体衬底10，绝缘层间组20（第一绝缘层间组），绝缘层间组30（第二绝缘层间组）和密封环40（保护环）。绝缘层间组20形成在半导体衬底10上。绝缘层间组30形成在绝缘层间组20上。绝缘层间组30由介电常数低于绝缘夹层组的绝缘材料形成密封环40设置成围绕电路形成区域D11和D12。密封环40穿过绝缘层间组20和绝缘层间组30之间的界面，并与半导体衬底10分开设置。

6. 发明申请

US20070018326A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070018326A1
公开(公告)日：2007-01-25
申请号：US11485438
申请日：2006-07-13
申请人： Mieko Hasegawa , Yasutaka Nakashiba
发明人： Mieko Hasegawa , Yasutaka Nakashiba
IPC分类号： H01L23/52
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring). The insulating interlayer group 20 is formed on the semiconductor substrate 10. The insulating interlayer group 30 is formed on the insulating interlayer group 20. The insulating interlayer group 30 is formed by an insulating material having a lower dielectric constant than that of the insulating interlayer group 20. The seal ring 40 is provided so as to surround the circuit forming regions D11 and D12. The seal ring 40 penetrates through the interface between the insulating interlayer group 20 and the insulating interlayer group 30 and is provided apart from the semiconductor substrate 10.
摘要翻译：半导体器件1包括半导体衬底10，绝缘层间组20（第一绝缘层间组），绝缘层间组30（第二绝缘层间组）和密封环40（保护环）。绝缘层间组20形成在半导体衬底10上。绝缘夹层组30形成在绝缘层间组20上。绝缘层间组30由具有比绝缘层间组20的介电常数低的绝缘材料形成。密封环40设置成围绕电路形成区域D 11和D 12。密封环40穿过绝缘层间组20和绝缘层间组30之间的界面，并与半导体衬底10分开设置。

7. 发明授权

US07687918B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07687918B2
公开(公告)日：2010-03-30
申请号：US10740813
申请日：2003-12-22
申请人： Yorinobu Kunimune , Mieko Hasegawa , Takamasa Itou , Takeshi Takeda , Hidemitsu Aoki
发明人： Yorinobu Kunimune , Mieko Hasegawa , Takamasa Itou , Takeshi Takeda , Hidemitsu Aoki
IPC分类号： H01L23/48
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76808 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.
摘要翻译：本发明提供一种半导体器件，其包括具有显着改善的电迁移电阻和/或抗应力迁移电阻的金属互连。铜互连107包括硅 - 下部浓度区域104和设置在其上的硅固溶体层106。硅固溶层106具有这样的结构，其中将硅原子引入构成铜互连件107的晶格结构内，作为晶间点原子或取代原子被布置在晶格内。硅固溶层106具有其中保留铜（面心立方晶格;晶格常数为3.6埃）的晶格结构，而硅原子被引入作为晶间点原子或取代原子的结构。

8. 发明授权

US06350683B1 Method of forming a tungsten plug in a hole 有权
标题翻译：在孔中形成钨丝塞的方法
公开(公告)号：US06350683B1
公开(公告)日：2002-02-26
申请号：US09644044
申请日：2000-08-23
申请人： Mieko Hasegawa
发明人： Mieko Hasegawa
IPC分类号： H01L219763
CPC分类号： H01L21/28556 , H01L21/7684 , H01L21/76877
摘要： The present invention provides a method of forming a tungsten plug in a hole of an inter-layer insulator. The method comprises the steps of: forming at least a hole in an inter-layer insulator; forming a thin barrier layer on at least an inside face of a hole; carrying out a first chemical vapor deposition process for growing a micro crystal tungsten thin film on the thin barrier layer; carrying out a second chemical vapor deposition process for growing a tungsten layer from the micro crystal tungsten thin film, so that the tungsten layer fills the hole and also extends over a top surface of the inter-layer insulator; and carrying out a chemical mechanical polishing process for selectively removing the tungsten layer over the top surface of the inter-layer insulator and leaving the tungsten layer in the hole, thereby to form a tungsten plug in the hole, wherein the second chemical vapor deposition process is carried out at a substrate temperature of not less than 475° C. and at a growth chamber pressure in the range of 90 Torr to 150 Torr, so that the tungsten layer has a high film density.
摘要翻译：本发明提供了一种在层间绝缘体的孔中形成钨插塞的方法。该方法包括以下步骤：在层间绝缘体中形成至少一个孔; 在孔的至少内表面上形成薄的阻挡层; 进行用于在薄阻挡层上生长微晶钨薄膜的第一化学气相沉积工艺; 进行用于从微晶钨薄膜生长钨层的第二化学气相沉积工艺，使得钨层填充孔并且也延伸超过层间绝缘体的顶表面; 并进行化学机械抛光工艺，用于选择性地去除层间绝缘体的顶表面上的钨层，并将钨层留在孔中，从而在孔中形成钨塞，其中第二化学气相沉积工艺在不低于475℃的基板温度和90托至150托的范围内的生长室压力下进行，使得钨层具有高的膜密度。

9. 发明授权

US06100197A Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06100197A
公开(公告)日：2000-08-08
申请号：US415922
申请日：1999-10-12
申请人： Mieko Hasegawa
发明人： Mieko Hasegawa
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/302 , H01L21/304 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/3212 , H01L21/7684
摘要： There is provided a method of fabricating a semiconductor device, including the steps of (a) forming recesses at a surface of an underlying insulating film, (b) covering inner surfaces of the recesses and a surface of the underlying insulating film with a barrier film, (c) depositing a copper film over the barrier film to thereby fill the recesses with copper, and (d) applying chemical mechanical polishing (CMP) to the copper film through the use of inorganic slurry on the condition that a polishing load is equal to or smaller than 140 g/cm.sup.2 and a linear velocity at a center of a wafer is equal to or smaller than 0.1 m/s. Though a copper film tends to be peeled off after CMP has been applied thereto in a conventional method, the method ensures that a copper film is no longer peeled off even after CMP has been applied thereto.
摘要翻译：提供了一种制造半导体器件的方法，包括以下步骤：（a）在下面的绝缘膜的表面形成凹槽，（b）覆盖所述凹部的内表面和所述下面的绝缘膜的表面与阻挡膜，（c）在阻挡膜上沉积铜膜，从而用铜填充凹槽，以及（d）在抛光负载相等的条件下通过使用无机浆料对铜膜施加化学机械抛光（CMP）至小于140g / cm 2，并且晶片中心处的线速度等于或小于0.1m / s。尽管在常规方法中对其施加CMP之后，铜膜倾向于被剥离，但是该方法确保即使在施加CMP之后也不会剥离铜膜。

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